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| df00z | I'm new to all this stuff. Kinda toying around. I have some like reg arrays, 128 bits, 256 bits. I wanna map 0 to 0, 1 to 7, 2 to 15 and so on. Like memory allocation, 256 bits deep, 8 bits wide. Is there any intelligent way to do that in verilog 2005 or with yosys? SystemVerilog has 2d arrays that work well. reg [0:127] lut_l = | 04:41 |
|---|---|---|
| df00z | 128'h00070e091c1b1215383f363124232a2d; Basically I wanna make something like that accessible with lut_l[0] = 00, lut_l[1] = 07 and so on | 04:41 |
| df00z | Googling around I just see people cursing verilog 2005. I tried one solution I found to use wires and assign a 2d array of wires back to the 1d array, it does work but uses lots of resources it seems | 04:42 |
| df00z | I could build a 4x4 bit multiplier i guess, or like a precalculated multiplication table but it seems whack, should be easier | 04:43 |
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| df00z | I more or less figured it out. Can initialize a 2d array of 8 bits in an initial block. It won't look like BRAM though to the synth(probably expected) One can model something that looks like BRAM and do the same. For going the other direction, 1d to 2d...I'm writing a serializer\deserializer so I can just count bits and every 8 add 1 to a byte counter, no need to do anything else | 18:01 |
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