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| RowanG[m] | I'm looking at the DSP on the ECP5 | 08:39 |
|---|---|---|
| RowanG[m] | using the lattice document: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02205-1-2-ECP5-and-ECP5-5G-sysDSP-Usage-Guide.ashx?document_id=50469 | 08:39 |
| RowanG[m] | and I don't understand why there are 4 clock inputs | 08:39 |
| RowanG[m] | Does anyone know how that works? | 08:39 |
| RowanG[m] | The only thing I can imagine is allowing a single DSP to be used in 4 domains at the same time depending on clock enable. But that's not someting I have ever come across | 08:41 |
| mwk_ | the DSP has 4 registers: A, B, pipeline, output | 10:44 |
| mwk_ | each of them can have independent CLK/CE/RST | 10:44 |
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