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| radens` | Hello! I'm trying to learn verilog and wanted to generate something like a circuit diagram to make sure I'm understanding everything. I did a ripple carry adder tutorial on eda and then I read that I could use a command like `yosys ./rcc.v -p 'show -prefix rcc -colors 2 -width -format dot'` to generate a diagram, but I don't see the outputs of | 18:56 |
|---|---|---|
| radens` | the tff blocks(wrong word?) being forwarded to the next blocks: https://imgur.com/a/2q5RSOK | 18:56 |
| tpb | Title: Imgur: The magic of the Internet (at imgur.com) | 18:56 |
| radens` | Tutorial in question: https://www.edaplayground.com/s/example/351 | 18:56 |
| tpb | Title: Ripple Carry Counter - EDA Playground (at www.edaplayground.com) | 18:56 |
| radens` | I was hoping to generate a diagram like the first frame of this video: https://www.youtube.com/watch?v=eXb8prknDKg&list=PLntFkFHRTxmLEv5MJN3oDvhd-5z3L5Rhi | 18:58 |
| radens` | What I got feels more like an ast. | 18:58 |
| Forty-Bot | radens`: use heirarchy first | 19:47 |
| Forty-Bot | so like `hierarchy -top ripple_carry_counter; prep; opt; show` | 19:47 |
| radens` | Forty-Bot that's more like it, thanks | 19:52 |
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