Sunday, 2022-07-17

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josuahikskuh: hello! late answer, sorry... I had some troubles with verilog features not being supported by yosys14:32
josuahso eventually there will be warnings issued14:32
josuahif you suspect one signal in particular, you could also inspect the """ "bits": { 1, 2, 2, 3, 3, 3, 3 }, """ (example numbers) sections of the verilog file14:34
josuahif instead of numbers, there are """ "bits": [ "x", "x", "x" ] """, but the signal should be used, maybe something wrong did happen14:35
josuahin that case, upgrading yosys could eventually help14:35
ikskuhjosuah: thanks, i figured it out14:42
ikskuhi was ... quite stupid :D14:42
ikskuhwhat also happened was that the bram took some clocks to be initialized14:42
ikskuhso the first memory fetch was still 014:42
josuahI am not sure I could figure as much :) glad it did!14:45
ikskuhyeah, i'm pretty good at debugging random shit ^^14:52
ikskuhlogic analyzer with 8 bit output is quite helpful14:52
ikskuhlast thing i logged was just the data on the bus14:52
ikskuhand i recognized "B7" which was the second data word14:52
ikskuhand before that was "00" which was definitly not what i was expecting14:52
ikskuhintroducing a 3 clock delay and it worked14:53
josuahin the various tooling for HDL, I see a lot of coverage for the happy path, but not so much for the "oops, that went unexpected"15:23
josuahlike large complex verification libraries and ecosystem15:24
josuahbut what if you need to debug a bug *through* all of these layers, with no idea on which layer it might be15:24
josuahfor that, having a very thin layer and tools targetted at inspection help15:25
josuah> logic analyzer15:26
josuahlike this :)15:26
josuahikskuh: may I ask which one do you have?15:26
josuahI had not much luck with sigrok on my side15:26
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ikskuhi have a cheap SALEAE clone15:44
ikskuh80€ with shipping from aliexpress15:44
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