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| josuah | hello! I am trying to get yosys talk SystemVerilog interfaces | 16:04 |
|---|---|---|
| josuah | but it looks like the signals got stuck in traffic | 16:05 |
| josuah | looking at my generated synthesis.json, I see plenty of list of signals (bit per bit) for plenty of things: | 16:05 |
| josuah | such as: "gpio_rgb": { "direction": "output", "bits": [ 5, 6, 7 ] }, ... | 16:06 |
| josuah | when I instanciate an interface on a module ("iSpi spi ();"), it is happy and fils all the "bits" everywhere on that module | 16:08 |
| josuah | but when I pass that instanciated interface to a submodule, the bits become "x", "x", "x", "x" | 16:08 |
| josuah | Verilator is not reporting anything going wrong, and the simulation runs fine | 16:08 |
| josuah | so I wonder: is it known that SystemVerilog interfaces are not there yet in yosys? Then I could try to look what I could eventually do. | 16:09 |
| josuah | or if they are reported to work, I can dig deeper onto my own verilog source. | 16:09 |
| josuah | if this message falls in the abyss of the backlogs of everyone, I will report a proper issue on the repo anyway... | 16:10 |
| josuah | thank you everyone! | 16:10 |
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| josuah | related: https://github.com/YosysHQ/yosys/issues/1592 | 16:36 |
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