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| ikskuh | heya o/ is this the right channel to ask some questions about pico rv32? | 09:36 |
|---|---|---|
| jix_ | ikskuh: yeah, I'm not aware of any channel specific to picorv32 | 10:21 |
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| ikskuh | ah, thanks | 11:06 |
| ikskuh | i figured i'm probably yeeting my own cpu design from my project and replace it with the picorv | 11:07 |
| ikskuh | mostly because of compilers and general slowness of my isa | 11:07 |
| ikskuh | but my system is designed for a 16 bit data bus right now, and i wonder if it's worth the change to blow up the data bus to 32 bit... | 11:08 |
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| acathla | Hi. I have a design that is using 98% of the ICESTORM_LC of an iCE40up5K, and building fine ith yosys 0.15. With yosys 0.16 and later it takes 108% LC and, of course, fails. Where should I look to find the right option that would allow me to not get stuck to 0.15? | 11:39 |
| tnt | -no-rw-check | 11:40 |
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| jix | Note that using that option (or older yosys versions) can result in a mismatch between synthesized behavior and simulation in certain cases. Probably fine on an existing working design, but good to be aware of | 11:54 |
| jix | You can also use (* no_rw_check *) as attribute on memories, which makes it easier to only omit the extra logic in cases where you made sure that it doesn't make a difference | 11:59 |
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| acathla | tnt, jix, thank you, that seems to work fine now ! | 15:02 |
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| tnt | I'm still a bit unclear as to what logic yosys in inserting TBH ... | 15:21 |
| tnt | I did a synht_ice40; write_verilog; to try and see but it's not making any sense to me. | 15:24 |
| tnt | But in any case just looking at it, I'm fairly certain it's not strictly correct either on ice40. Because a R/W conflict is defined there as a read and write to the same address for the underlying RAM4k module which is always 16 bit wide and not for the wrapper above it that allows 1/2/4/8/16 bits accesses. | 15:30 |
| tnt | (i.e. technically for a 8 bits wide ram, a read access at address 0 and a write to address 1 is a conflict. | 15:30 |
| jix | I haven't looked at the specifics at all, but even if a read access to address 0 and a write to address 1 conflict on the underlying primitive, in that case you get the same result independent of whether the primitve reads the new or the old value, because for the read byte they are the same, right? | 17:24 |
| tnt | Ah but the official sim model doesn't specify read-first or write-first behavior. It specifies xxxx as output in case of conflict. | 17:26 |
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| jix | ah, in that case that does seem like an issue to me | 17:46 |
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