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| corecode | oh i didn't realize that yosys can synthesize for efinix fpgas | 13:58 |
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| rowang077[m] | What are "SIOLOGIC" resources? | 17:04 |
| rowang077[m] | I find I use quite a few of them in my design | 17:04 |
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| rowang077[m] | Specifically for ECP5 | 17:09 |
| rowang077[m] | in the ECP5 high-speed IO manual I can find that there is a difference between IOLOGIC and SIOLOGIC | 17:09 |
| rowang077[m] | s/ECP5/ECP3/ | 17:09 |
| rowang077[m] | But there is no mention of them in the same document for ECP5 | 17:10 |
| gatecat | SIOLOGIC are for the top/bottom sides, IOLOGIC are for the left/right sides | 17:16 |
| gatecat | no idea what 'S' stands for, you'd have to ask lattice :D | 17:16 |
| gatecat | they'll be used for each pin that has a DDR I/O or a packed I/O register | 17:16 |
| rowang077[m] | Ah allright | 17:17 |
| rowang077[m] | so there is no (known) functional difference between IOLOGIC and SIOLOGIC? | 17:17 |
| rowang077[m] | it's just different locations on the fabric | 17:17 |
| gatecat | the IOLOGIC are more feature-complete | 17:17 |
| gatecat | but which of the two are used depend on the IO pin you're using | 17:18 |
| gatecat | the [S]IOLOGIC blocks are directly tied to a specific IO | 17:18 |
| rowang077[m] | Clear. Thx! | 17:19 |
| rowang077[m] | Do you now how I can understand why a asynchronous path is seen in nextpnr | 17:25 |
| rowang077[m] | From what I can tell in my code there shouldn't be an async path | 17:25 |
| rowang077[m] | I have uploaded the code here: https://gist.github.com/rowanG077/7b5c561c88c2e5a1873802fbd4716bbe | 17:30 |
| rowang077[m] | But it's generated so it's not to easily readable | 17:30 |
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| gatecat | I think it's something to do with how the DIRECTION pin on the iodelay has been implemented# | 18:43 |
| gatecat | inside nextpnr | 18:43 |
| gatecat | not anything to worry about - tbh the async paths aren't that meaningful in general atm | 18:44 |
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