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| cr1901 | If I have a design with a single clock, and most of the design is gated by a clock-enable that only asserts every "n" cycles 1/2 | 22:42 |
|---|---|---|
| cr1901 | Is there a way to tell nextpnr to treat the max freq of everything gated by that clock enable as clk_freq/n? | 22:42 |
| cr1901 | Use case- I want a 48MHz and 16MHz clock from a 12MHz input, but only have one PLL | 22:43 |
| cr1901 | So my idea was to generate the 48MHz clock directly and then clock en to simulate a 16MHz clock | 22:44 |
| cr1901 | Alternate solutions welcome, maybe I missed something about the ice40 PLL | 22:45 |
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