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Guest57 | i'm running `synth -top $::env(DESIGN_NAME) {*}$::env(SYNTH_ARGS)` and crapping out at the abc step | 20:29 |
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Guest57 | i've been trying to figure out how to recover the state that `synth -top $::env(DESIGN_NAME) {*}$::env(SYNTH_ARGS) -noabc` induces | 20:29 |
Guest57 | so that i can restart the flow from just there | 20:29 |
Guest57 | but there's so much state in context and design and env variables and etc | 20:30 |
Guest57 | i tried `write_verilog/read_verilog` and `write_blif/read_blif` as checkpoints | 20:30 |
Guest57 | but that doesn't work either | 20:30 |
mithro | People here might find this post interesting, from Xilinx's CTO - https://www.linkedin.com/pulse/chips-alliance-fpga-interchange-format-ivo-bolsens/?trackingId=D2msEW1%2FThmTehF86lCZ2Q%3D%3D | 20:55 |
tpb | Title: CHIPS Alliance FPGA Interchange Format (at www.linkedin.com) | 20:55 |
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