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| thezoq2 | Is it possible to make yosys infer block rams when using "vector bit-select and part-select addressing" https://stackoverflow.com/questions/18067571/indexing-vectors-and-arrays-with#18068296 | 15:36 |
|---|---|---|
| thezoq2 | I'm running it on some code which looks like | 15:36 |
| tpb | Title: system verilog - Indexing vectors and arrays with +: - Stack Overflow (at stackoverflow.com) | 15:36 |
| thezoq2 | ``` | 15:36 |
| thezoq2 | always @(posedge clk) begin | 15:36 |
| thezoq2 | array[widx * 32 +: 32] = new_val; | 15:36 |
| thezoq2 | out = array[ridx * 32+:32]; | 15:36 |
| thezoq2 | end | 15:36 |
| thezoq2 | ``` | 15:36 |
| thezoq2 | But it's not inferring it as block ram. Changing `array` to be a unopacked array works, but as I'm writing a compiler, it would be much more convenient for me to only work with packed arrays. | 15:36 |
| gatecat | no, as far as I know the way the Yosys verilog frontend is written means that you have to use unpacked arrays if you want memory to be inferred | 15:38 |
| thezoq2 | Alright, thanks! | 15:42 |
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