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| ikskuh | oh god | 20:02 |
|---|---|---|
| ikskuh | verilog simulation is having race conditions? | 20:03 |
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| killjoy | Never underestimate the lowest common denominator. | 20:28 |
| killjoy | (This is regards to krb asking about musical synthesizers.) | 20:28 |
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| lofty | So, could somebody better at Verilog than me tell me if signedness matters for a reduce-AND (unary &) | 20:57 |
| lofty | e.g. if there's a case where `&$signed(X) != &$unsigned(X)` | 20:57 |
| lofty | Because I don't think there is but I'm not a language lawyer | 20:58 |
| lofty | (this is relevant because Yosys has an input signedness parameter to $reduce_and) | 20:58 |
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