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| somlo | trying to build yosys v13 for Fedora (with mock), and `make manual` fails: https://pastebin.com/59mWyg6X | 01:05 |
|---|---|---|
| tpb | Title: ...make[1]: Leaving directory '/builddir/build/BUILD/yosys-61324cf55fc5c523716 - Pastebin.com (at pastebin.com) | 01:05 |
| somlo | I can open a github issue, but wondering if more details would be preferred beyond just "it breaks when I run make manual, here's the log" :) | 01:06 |
| somlo | if so, any advice appreciated, TIA | 01:08 |
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| sagar_acharya | Sarayan: Are you there? | 05:27 |
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| sagar_acharya | What is a monochrome digital signal? wrt video output signal? | 05:31 |
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| xiretza[m] | <sagar_acharya> "What is a monochrome digital..." <- you have a single bit of video data, aka monochrome | 06:44 |
| xiretza[m] | if you want 0 to be black and 1 to be white, you need to hook it up to all the VGA color bits | 06:44 |
| sagar_acharya | How do I convert it to rgb | 06:44 |
| sagar_acharya | Aah alright | 06:44 |
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| xiretza[m] | you can also hook it up to any other combination of color bits for funkier colours than white ;) | 06:45 |
| sagar_acharya | For now, I'll just go with b&w but so, it runs across complete screen and assigns it rgb? | 06:46 |
| sagar_acharya | So, if I just assign rgb values of black to 0 of video and rgb values of white to 1 of video signal | 06:46 |
| sagar_acharya | That should do it right? | 06:47 |
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| xiretza[m] | if I understood you correctly, that should do it | 06:47 |
| sagar_acharya | xiretza: ok, on it, thanks. | 06:48 |
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| sagar_acharya | I have this iCE40HX8KPinout.ods | 08:28 |
| sagar_acharya | https://github.com/OLIMEX/iCE40-IO/blob/master/ICE40-IO_Rev_A.pdf | 08:29 |
| sagar_acharya | And I have the above pin diagram for VGA. How do I determine which port of vga is connected to which pin? | 08:30 |
| sagar_acharya | https://notabug.org/sagaracharya/swarajya/raw/master/iCE40PinoutHX8K.ods | 08:30 |
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| Sarayan | you're missing the board schematic that tells you which fpga pin goes to which gpio pin | 09:03 |
| lambda | they disconnected | 09:03 |
| Sarayan | true, damn | 09:04 |
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| lambda | sagar_acharya: welcome back | 10:10 |
| lambda | still stuck? | 10:10 |
| sagar_acharya | yes | 10:10 |
| lambda | let's take VGA_BLUE1 for example. From the iCE40-IO schematic, you can see it's connected to pin 26 on the extension header. Then you look at the schematic for your board (https://github.com/OLIMEX/iCE40HX8K-EVB/blob/master/HARDWARE/REV-B1/iCE40HX8K-EVB_Rev_B1.pdf), which tells you that pin 26 on the extension header is connected to PIO3_19/IOL_10B, and if you follow that (19th pin on bank 3), it's | 10:10 |
| lambda | connected to ball F1 on the FPGA - that's your ball number. Could've also done that last step with your spreadsheet, it tells you that IOL_10B is ball F1. | 10:10 |
| sagar_acharya | I got the first part. Thanks a lot. | 10:14 |
| sagar_acharya | I don't get 19th pin on bank 3 | 10:14 |
| sagar_acharya | I have the sheet, so what is ball, bank and those codes DPIO? | 10:15 |
| sagar_acharya | What do they mean. | 10:15 |
| sagar_acharya | ? | 10:15 |
| sagar_acharya | I'll just assume ball is another name for pin | 10:15 |
| lambda | your FPGA is in a BGA package - it doesn't have pins, it has a grid of balls | 10:16 |
| sagar_acharya | What is BGA? | 10:17 |
| lambda | https://en.wikipedia.org/wiki/Ball_grid_array | 10:17 |
| tpb | Title: Ball grid array - Wikipedia (at en.wikipedia.org) | 10:17 |
| sagar_acharya | Alright nice, got it. | 10:18 |
| sagar_acharya | I would just call them 2D small pins though | 10:18 |
| sagar_acharya | They're just metal contacts in my view. | 10:18 |
| sagar_acharya | Unnecessary added nomenclature here by some folk. | 10:18 |
| lambda | sure, whatever, I'm just trying to not get them confused with the pins on the expansion header :p | 10:18 |
| sagar_acharya | Alright! :D , got it! | 10:19 |
| sagar_acharya | lambda: Thanks man! | 10:19 |
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| ikskuh | heya o/ | 10:49 |
| ikskuh | is it okay to ask people here for reviewing my code? i don't need a in-depth analysis or whatever, but just some eyeballing for low hanging fruits | 10:50 |
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| lofty | ikskuh: sure | 11:17 |
| ikskuh | ah, very nice <3 | 11:23 |
| ikskuh | i'll ask again when i'm done with what i'm doing right now | 11:23 |
| ikskuh | how typical is a non-clocked process? | 11:23 |
| lofty | ikskuh: combinational processes are pretty common for obvious reasons. | 11:40 |
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| ikskuh | ah | 11:51 |
| ikskuh | so implementing a mux4 would probably a good choice for a process then? | 11:51 |
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| sagar_acharya | https://github.com/OLIMEX/iCE40HX8K-EVB/blob/master/demo/ice40-io-video/ice40-io-video.pcf | 12:06 |
| sagar_acharya | This has 9 outputs of 3 bit 3 rgb values. | 12:07 |
| sagar_acharya | However, vga cable has just 3 connectors for rgb. | 12:07 |
| sagar_acharya | https://en.wikipedia.org/wiki/VGA_connector | 12:07 |
| tpb | Title: VGA connector - Wikipedia (at en.wikipedia.org) | 12:07 |
| sagar_acharya | Are they sent serially? | 12:07 |
| sagar_acharya | https://github.com/OLIMEX/iCE40-IO/blob/master/ICE40-IO_Rev_A.pdf | 12:08 |
| sagar_acharya | And above schematic shows that the line passes through 3 different registers of 470, 1k and 1.8k units. | 12:09 |
| sagar_acharya | I don't get this! | 12:09 |
| tnt | it's a basic resistor DAC. | 12:12 |
| Sarayan | resistors, not registers | 12:13 |
| Sarayan | vga r/g/b is analog, these resistor dacs given you 8 analog levels | 12:13 |
| sagar_acharya | sorry yeah resistors | 12:14 |
| sagar_acharya | I meant resistors there | 12:14 |
| sagar_acharya | Ah alright. | 12:15 |
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| sagar_acharya | Wooh, I got a blinking cursor folks! | 12:51 |
| sagar_acharya | I still can't get any input from keyboard though! | 12:58 |
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| somlo | re. broken `make manual` (https://pastebin.com/59mWyg6X) -- I have opened issue 3156 with steps to reproduce; | 16:01 |
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