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| ikskuh | hmm | 19:31 |
|---|---|---|
| ikskuh | i've got a sticky reg and i have no idea why it sticks | 19:32 |
| ikskuh | how could i debug this? | 19:32 |
| lambda | what's a sticky reg? | 19:32 |
| ikskuh | i have a "reg vsync" | 19:32 |
| ikskuh | which i assign 0 in reset, and have two conditions where one sets it to 1 and the other sets it to 0 | 19:32 |
| ikskuh | but the set to 0 never seems to happen | 19:32 |
| lambda | in hardware or in simulation? | 19:33 |
| ikskuh | hw | 19:33 |
| ikskuh | simulation is next /o\ | 19:33 |
| ikskuh | i really should simulate before i prog | 19:33 |
| lambda | yeah, try that, also make sure you're meeting timing | 19:33 |
| ikskuh | i have pll to 160 mhz, synthesis tells me 296 mhz should be good | 19:34 |
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| ikskuh | oh yeah, 25 MB vcd file \o/ | 19:40 |
| lambda | that's pretty compact! | 19:40 |
| ikskuh | heh | 19:41 |
| ikskuh | i'm trying to implement VGA (again) | 19:41 |
| ikskuh | have done it successfully in VHDL already | 19:41 |
| ikskuh | but learning the whole yosys+iverilog way right now | 19:41 |
| lambda | that's always fun to implement :) and it's fairly easy to slap DVI/HDMI on top, too | 19:42 |
| ikskuh | yeah | 19:46 |
| ikskuh | i wanna built my own computer and stuff | 19:46 |
| ikskuh | i've learnt that DVI is just serial VGA | 19:46 |
| ikskuh | huh, weird | 19:49 |
| ikskuh | it's also sticky in the sim | 19:49 |
| lambda | hooray, much easier to debug! :) | 19:49 |
| ikskuh | localparam vga_vs_end = vga_height + vga_hs_frontporch + vga_vs_syncpulse; | 19:50 |
| ikskuh | reading code would've helped too /o\ | 19:51 |
| ikskuh | that was one heck of a stupid mistake | 19:51 |
| lambda | oh, whoops | 19:51 |
| ikskuh | let's see what happens when i now measure ^^ | 19:52 |
| ikskuh | screen is white \o/ | 20:08 |
| lambda | cool! | 20:09 |
| ikskuh | now let's do colors! | 20:10 |
| ikskuh | https://mq32.de/public/9a0bb99965048871e98672449936078d6834d266.jpg | 20:20 |
| ikskuh | works | 20:20 |
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