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| ikskuh | heya o/ | 16:22 |
|---|---|---|
| ikskuh | Warning: Replacing memory \data with list of registers. See src/fifo.v:54, src/fifo.v:48 | 16:22 |
| ikskuh | is that a bad thing? | 16:22 |
| xiretza[m] | depends on how big your memory is | 16:24 |
| ikskuh | 64 bit in that case | 16:24 |
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| xiretza[m] | might be fine then, it should tell you somewhere why it's not using block RAM | 16:28 |
| xiretza[m] | might just be too small to bother | 16:28 |
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| ikskuh | is block ram automagically deduced? | 16:30 |
| xiretza[m] | well, yosys tries to do that, but it's not always very good at it | 16:33 |
| ikskuh | ah, thanks :) | 16:35 |
| ikskuh | both Verilog and yosys is very new to me | 16:35 |
| ikskuh | i have some experience with Lattice Diamond and MachXO{1,2,3} | 16:36 |
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| ikskuh | i should learn how to run a simulation/workbench ^^ | 16:53 |
| ikskuh | "my code doesn't work, it needs debugging" | 16:53 |
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