Monday, 2021-12-13

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bluesceadaxiretza[m], yeah but we wanted to have an open-source toolchain, or is there vhdl support in yosys by now? I personally also learned VHDL before verilog, but I like verilog more by now. If it has enough errors/warnings it should also be fine, imho08:09
bluesceadalofty, thanks, I will have a look. But I guess that will not make the warning an error?08:10
tntThere is a ghdl plugin for yosys to add vhdl support.08:12
bluesceadatnt, the last time I tried that didn't really work well08:13
tntHeh, no idea, never tried it ...08:13
bluesceadaanyway, because that was the case, we changed all our experiments from vhdl to verilog ... that was 2-3 years ago or so08:14
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loftybluesceada: yes, it makes it an error10:39
lofty    -e regex10:40
lofty        if a warning message matches the regex, it is printed as error10:40
lofty        message instead and the tool terminates with a nonzero return code.10:40
bluesceadalofty, ah thanks, that's nice10:41
bluesceadabut something like -Werror (makes all warings errors) is not available?10:44
tntthat'd be useless really because some warning can't be suppressed and are perfectly valid verilog.10:46
tnt(the "converting to multiple register" thing when using arrays comes to mind.)10:48
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bl0x@bluesceada last time I tried the ghdl plugin for yosys it was working fine. I used it with apio then.11:48
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xiretza[m]<bluesceada> "tnt, the last time I tried..." <- I can agree with bl0x there, it works pretty well nowadays11:57
gatecatime if you do hit specific bugs they are fixed pretty quick too12:00
gatecatat least when I last played with it12:00
bluesceadaah ok, thanks, but yeah too late for now, our experiments evolved since they got converted to verilog12:01
bluesceadaand probably it would be more effort than just installing oss-cad-suite ? which is better to support the students when it is just a single install...12:01
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