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bosje | Hi, any suggestions for getting around this error: | 11:59 |
---|---|---|
bosje | `ERROR: Unsupported expression on dynamic range select on signal \a` | 11:59 |
bosje | ```verilog | 11:59 |
bosje | generate | 11:59 |
bosje | for (i = 0; i < 10; i = i + 1) begin | 11:59 |
bosje | MyModule u_temp (.x(a[i][0], .y(~a[i][1])); | 11:59 |
bosje | end | 11:59 |
bosje | endgenerate | 11:59 |
bosje | ``` | 11:59 |
bosje | Guess you can't access specific bits in a for generate loop? | 12:00 |
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bosje | anyone know how to turn off synthesis optimizations? | 16:17 |
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lofty | bosje: which synth script? | 16:28 |
bosje | custom one: | 16:28 |
bosje | ``` | 16:28 |
bosje | synth -top $top | 16:28 |
bosje | dfflibmap -liberty $lib_lib | 16:28 |
bosje | abc -liberty $lib_lib | 16:28 |
bosje | ``` | 16:28 |
lofty | bosje: add -fast to abc | 16:28 |
bosje | what will that do? | 16:29 |
lofty | turn off synthesis optimizations | 16:29 |
bosje | awesome, thanks | 16:29 |
lofty | -fast is basically "map as-is" | 16:29 |
bosje | will it still do SAT reduction? | 16:30 |
lofty | no, but it will structual hash | 16:30 |
lofty | *structural hash | 16:30 |
bosje | Let me experiment a bit, I found that sometimes the optimizations reveal other bugs | 16:31 |
bosje | i have to basically handcraft the netlist anyway for what I am trying to do | 16:31 |
lofty | structural hashing is unlikely to cause that | 16:31 |
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