Tuesday, 2021-11-30

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bosjeHi, any suggestions for getting around this error:11:59
bosje`ERROR: Unsupported expression on dynamic range select on signal \a`11:59
bosje```verilog11:59
bosjegenerate11:59
bosje  for (i = 0; i < 10; i = i + 1) begin11:59
bosje    MyModule u_temp (.x(a[i][0], .y(~a[i][1]));11:59
bosje  end11:59
bosjeendgenerate11:59
bosje```11:59
bosjeGuess you can't access specific bits in a for generate loop?12:00
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bosjeanyone know how to turn off synthesis optimizations?16:17
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loftybosje: which synth script?16:28
bosjecustom one:16:28
bosje```16:28
bosjesynth -top $top16:28
bosjedfflibmap -liberty $lib_lib16:28
bosjeabc -liberty $lib_lib16:28
bosje```16:28
loftybosje: add -fast to abc16:28
bosjewhat will that do?16:29
loftyturn off synthesis optimizations16:29
bosjeawesome, thanks16:29
lofty-fast is basically "map as-is"16:29
bosjewill it still do SAT reduction?16:30
loftyno, but it will structual hash16:30
lofty*structural hash16:30
bosjeLet me experiment a bit, I found that sometimes the optimizations reveal other bugs16:31
bosjei have to basically handcraft the netlist anyway for what I am trying to do16:31
loftystructural hashing is unlikely to cause that16:31
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