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| pepijndevos[m] | I've started a page on the Yosys wiki with the goal of documenting which FPGA families support which primitives. I've added Apicula, which I maintain, so if people think it's a good idea it could also contain other FPGA projects. https://github.com/YosysHQ/yosys/wiki/FPGA-family-feature-matrix | 18:49 |
|---|---|---|
| Sarayan | what's a long wire? | 18:51 |
| pepijndevos[m] | Some FPGAs have wires that cross a significant part of the grid, rather than going to adjacent tiles. | 18:51 |
| Sarayan | oh, and they're special? | 18:53 |
| sorear | i predict that table will grow a lot of rows and n/a cells, as well as debate over whether feature X in fpga Y actually corresponds to table row Z | 18:54 |
| Sarayan | (wire length in the cyclone v can be 2, 3, 4, 6, 12 or 14 tiles, there's not really any distinction) | 18:55 |
| Sarayan | die tile size goes from 49x40 up to 122x116 just to put things in perspective | 18:56 |
| Sarayan | clock grid has bigger stuff, including 16 global clocks that go just everywhere | 18:56 |
| Sarayan | it's funky stuff :-) | 18:57 |
| pepijndevos[m] | Hmmm yea the table items will have to evolve to accomodate what FPGA families actualy have | 19:00 |
| pepijndevos[m] | I'm fine with folding long wires under global/clock routing | 19:01 |
| whitequark | even ice40 has long wires (span4/span12) | 19:12 |
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| cr1901 | Can we have a yellow "caution" symbol for "it should work but not well-tested"? | 19:31 |
| pepijndevos[m] | Sure | 19:35 |
| pepijndevos[m] | Should also have a "partial" symbol probably | 19:35 |
| cr1901 | traffic cone? | 19:36 |
| pepijndevos[m] | ohhhh yea | 19:36 |
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| cr1901 | pepijndevos[m]: No traffic cone emoji. This is close enough IMO | 19:41 |
| cr1901 | https://github.com/iximeow/yaxpeax-arch | 19:41 |
| cr1901 | See the symbols | 19:42 |
| pepijndevos[m] | nice | 19:42 |
| cr1901 | I updated the page | 19:49 |
| pepijndevos[m] | awesome looks good! | 19:52 |
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