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| bluesceada | There is a problem with newer yosys versions when accessing regs like din[(i<<3)+:8] ... while din[(i*8)+:8] works correctly | 13:27 |
|---|---|---|
| bluesceada | it also worked in older yosys versions (some version from FPGAwars from 2019), but not in the recent ones included in oss-cad-suite over the last 6 months or so | 13:28 |
| bluesceada | We might bisect this when we find time, but not now .. | 13:28 |
| mwk | do you have a sample? | 13:28 |
| mwk | (I dont' mind looking at a huge one) | 13:28 |
| bluesceada | not sure if I should just give that out, let's see... | 13:30 |
| mwk | can you reduce it to something you can show me? | 13:30 |
| bluesceada | Not now, but I can only give it to you, should just not be totally public here | 13:31 |
| bluesceada | mwk, I can send you the link in query | 13:33 |
| tnt | How recent is recent ? | 13:39 |
| tnt | I'm testing https://pastebin.com/rEpy6WZ9 | 13:39 |
| tpb | Title: module test( input wire [31:0] a, input wire [1:0] b, output w - Pastebin.com (at pastebin.com) | 13:39 |
| mwk | right, hold on | 13:40 |
| mwk | this is one of these unfortunate moments when I have to consult the Verilog standard to figure out if it's really a bug, or just a correctly implemented Verilog pitfall | 13:40 |
| tnt | yosys's behavior is correct from my reading. | 13:46 |
| mwk | yeah, mine as well | 13:47 |
| mwk | this is a Verilog pitfall IMO | 13:47 |
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| mwk | don't see the exact place in Verilog standard where it says that bit select index width is self-determined, but I don't really see it being any other way | 13:48 |
| bluesceada | The question is if you want to handle it like a commercial tool as lattice icecube, or not | 13:51 |
| bluesceada | We might have also used this in Xilinx Vivado successfully (but not sure) | 13:51 |
| tnt | mwk: mmm, I guess 'integer expression' could mean 32b. | 13:52 |
| bluesceada | but yeah if you write (b << 3) ... I guess one should not expect an automatic bit width extension of b --- that is also why we realized quite quickly that this could be a problem | 13:54 |
| mwk | current yosys behavior is correct, I'm afraid | 13:56 |
| bluesceada | That's one of the situations in which VHDL's strictness is better, I guess | 13:56 |
| mwk | "like a commercial tool" is ill-defined in the first place | 13:56 |
| bluesceada | mwk, of course, I have no specific opinion on this, I am not saying yosys should change it | 13:56 |
| mwk | I can take a bet there's a different commercial tool that behaves like yosys does | 13:56 |
| mwk | ... this is the usual outcome of attempting to use many parts of Verilog | 13:57 |
| bluesceada | Yes, icecube isn't really widely used | 13:57 |
| bluesceada | If widely used tools of Xilinx/Intel/Synopsys/Cadence/Mentor would do the extension in the index I would say yosys should be too (if the Verilog standard is not 100% clear on that) | 13:58 |
| mwk | okay | 13:58 |
| mwk | Verilog standard wasn't helpful | 13:58 |
| mwk | but SystemVerilog is very clear on this | 13:58 |
| bluesceada | is there a way to set which standard to follow in yosys? many commercial tools often have that option | 13:59 |
| mwk | "The bit can be addressed using an expression that shall be evaluated in a self-determined context." | 13:59 |
| mwk | not really, no | 13:59 |
| mwk | there's an option to enable or disable systemverilog, but it basically just disables features, it doesn't *change* anything | 14:00 |
| mwk | also: given that Verilog has no text at all on the subject, but also absolutely no reason to infer anything but self-determined behavior by default, I'm just going to go with the "it should always be self-determined" interpretation | 14:01 |
| mwk | SystemVerilog text clarifying the intended meaning | 14:02 |
| bluesceada | so and for you "self-determined" means to not extend the width? That doesn't sound clear to me, to be honest | 14:02 |
| mwk | that's an actual well-defined term from the standard | 14:03 |
| bluesceada | OK | 14:03 |
| mwk | for a shift expression like this, it very definitely means the width is taken directly from left operand | 14:03 |
| bluesceada | ok good | 14:04 |
| bluesceada | thanks for your help | 14:05 |
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| cr1901 | Yea, I uhhh... optimized the uart miter down to a minimal example. I don't think I'm going to make it pass lmao: https://github.com/cr1901/yosys-experiments/tree/master/sat/dffhold | 16:28 |
| cr1901 | (This was written as a minddump, sorry if the README is hard to follow) | 16:28 |
| cr1901 | Also... did... did symbiyosys always have an "equiv" mode? | 16:31 |
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