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| cr1901 | read_verilog only works for full modules. Is it possible to take a selection and create a separate module so that I can write out the subset of the entire input cone of an output signal as a module? | 02:13 |
|---|---|---|
| mwk | design -save, flip selection, remove selection, write what remains to .v file, design -load | 02:28 |
| mwk | (assuming you mean write_verilog) | 02:28 |
| cr1901 | Yes write_verilog is what I meant | 02:29 |
| cr1901 | I came across a design that synthesizes for machxo2 but the post-synth doesn't match pre-synth. And I got a miter to fail induction w/ the desired signal | 02:30 |
| mwk | ... that's worrying | 02:30 |
| cr1901 | It's probably something I did | 02:30 |
| mwk | how exactly are you doing the post-synth test? | 02:31 |
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| cr1901 | https://github.com/YosysHQ/nextpnr/blob/master/machxo2/examples/mitertest.sh#L54-L69 | 02:31 |
| cr1901 | You want me to give you my exact inputs? | 02:31 |
| mwk | mhm, so it's not a P&R issue, okay | 02:32 |
| cr1901 | Right, this happens during packing | 02:32 |
| cr1901 | sorry for not making that clear | 02:32 |
| mwk | packing? | 02:33 |
| cr1901 | FFs/LUTs => SLICEs | 02:33 |
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| mwk | oh, so you're tracking down a nextpnr bug? | 02:33 |
| cr1901 | yes | 02:33 |
| mwk | okay, was worried there was something broken in general yosys code for a moment | 02:34 |
| cr1901 | But Idk where to even look without using yosys to help me | 02:34 |
| cr1901 | There's no way I'm gonna be able to keep track of the entire post-synth design in my head, even for something as simple as a UART | 02:34 |
| mwk | ... last time I was in that situation, I ended up tracking down a JSON parser bug with an oscilloscope | 02:37 |
| cr1901 | That is one hell of a sentence you just wrote. | 02:38 |
| cr1901 | Anyways I'm giving up for the night | 02:40 |
| cr1901 | What are the commands for flipping/removing selection? And is the design -save part necessary? | 02:41 |
| mwk | design -save is only necessary if you want to get the original back later | 02:42 |
| mwk | the remove command is spelled `delete <selection>` | 02:42 |
| mwk | and as for flipping: append %n when constructing the selection | 02:42 |
| cr1901 | tyvm... night! :) | 02:45 |
| mwk | night | 02:48 |
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| famubu | Hi. Is yosys more comfortable working with verilog when compared to vhdl? Is there something like that? (I'm new to yosys) | 06:11 |
| famubu | The manual mentions in the history section of the yosys manual that the developers prefered verilog over vhdl. | 06:12 |
| famubu | And in Chapter 4 (Implementation overview), it is mentioned that a VHDL frontend is in development. | 06:12 |
| famubu | Found https://github.com/YosysHQ/yosys-plugins/tree/master/vhdl | 06:13 |
| famubu | But the last commit was 6 years ago. | 06:13 |
| gatecat | famubu: https://github.com/ghdl/ghdl-yosys-plugin is considerably newer and more complete | 06:40 |
| famubu | gatecat: Thanks! | 06:43 |
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| cr1901 | Okay, I'm awake. And my current verdict is I don't want to work on finding the bug today. So I won't :). | 14:37 |
| cr1901 | Thank goodness for .yosys_history | 14:38 |
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