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| dormito | I've notice that when I do "read_verilog -sv ${verilog-source-file}" it prints "Executing Verilog-2005 frontend", and then seems to choke on any usage of interfaces (says the signals implicitly defined, eventhough it already parsed it in the module ports). Am I invoking systemverilog incorrectly? | 07:59 |
|---|---|---|
| Sarayan | the current sv parser has limits | 08:10 |
| dormito | the README.md says it supports interfaces and mod ports... is that qualified or incorrecT? | 08:12 |
| Sarayan | I'm not entirely sure of the limits, I know one is missing non-packed structures | 08:16 |
| Sarayan | but I'm certain it's not yet fully handling sv-for-synthesis | 08:16 |
| dormito | Hmmm maybe the readme should be updated then (since it seems to pretty clearly say some certain systemverilog features are supported). I've distilled the reproduction down to a 23-line hdl file anyone wants to see how to invoke it. | 08:21 |
| Sarayan | would probably be interesting to implement what's missing in that area | 08:24 |
| Sarayan | as far as I can tell it's a case of "nobody has implemented it yet", not something deliberate :-) | 08:24 |
| dormito | well, if anyone's interesting. The trivial reproducer I created is here: http://dpaste.com/6XUPYP9UA/ | 08:41 |
| tpb | Title: dpaste: stdin (at dpaste.com) | 08:41 |
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