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| lambda | holy mother of issue notifications | 10:08 |
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| mwk | yup | 11:13 |
| mwk | we figured we may try to enable the github discussions thing since so many issues are actually questions | 11:13 |
| mwk | this involved a little issue tracker sweep | 11:13 |
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| scientes | Are there any cycle-accurate FPGA simulators? | 20:23 |
| scientes | I want something like single-stepping gdb | 20:24 |
| scientes | just to get a better feel of these things | 20:24 |
| scientes | (obviously something small like a ice40) | 20:24 |
| agg | often you'd simulate your logic using a logic simulator, something like verilator, icarus verilog, modelsim, cxxrtl (built in to yosys), and often then use some tool to view the simulation results (like gtkwave) | 20:26 |
| agg | depending on what you need, you can simulate just your logic, or the result of synthesising it into FPGA elements, and include simulation models of the FPGA hardware like block memories, DSP units, etc | 20:26 |
| scientes | <agg> depending on what you need, you can simulate just your logic, or the result of synthesising it into FPGA elements, and include simulation models of the FPGA hardware like block memories, DSP units, etc | 20:26 |
| scientes | yeah, the ice40 is small enough you could simulate the whole thing | 20:27 |
| agg | if you're asking about simulating a physical specific ice40 chip and bitstream, not sure if such a thing really exists beyond wrapping the simulators I mentioned | 20:27 |
| agg | what are you trying to get a feel of exactly? | 20:27 |
| scientes | low-level synthesis | 20:27 |
| agg | you can dump the synthesis as verilog and simulate it with models of each primitive, the same way you'd simulate logic | 20:28 |
| scientes | like using codeexplorer | 20:28 |
| agg | and can include the timing information if you need to model that too, with some simulators, assuming you have that information | 20:28 |
| agg | but it seems like an unusual thing to go about doing, i feel like the objective is usually to simulate your design, not your fpga | 20:29 |
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| agg | (there are other physical simulation tools for asics I guess to cover things like antenna rules and power distro, I don't really know anything about them) | 20:29 |
| sorear | a fpga is an analog device, "cycle accurate" will always involve compromises | 20:35 |
| scientes | sorear, ahhh | 20:35 |
| scientes | its clocked so it appears a digital device only | 20:36 |
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