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| jonpry | Why would yosys/ABC give drastically different static timing results from OpenSTA? https://pastebin.com/ChXHa6r9 | 16:13 |
|---|---|---|
| tpb | Title: Yosys:ABC: WireLoad = "none" Gates = 31998 ( 38.7 %) Cap = 8.6 ff ( 12. - Pastebin.com (at pastebin.com) | 16:13 |
| tnt | because you're not looking at the same path at all ? | 16:17 |
| tnt | First one looks like a purely comb path across the design, the second looks like an internal FF -> FF path. | 16:18 |
| jonpry | It is a critical path report from each tool | 16:20 |
| jonpry | As I understand it, ABC stime removes the FF from the ends of path | 16:20 |
| tnt | Are you sure you even loaded the same process corners libraries ? | 16:21 |
| jonpry | Yes | 16:22 |
| tnt | And where is that OpenSTA from ? Is it post-synth ? Or post-pnr ? And setup with the same load and drive caracteristics ? | 16:23 |
| jonpry | It's post-synth. Right after yosys does the stime, i write out and run it through opensta | 16:25 |
| jonpry | I have not setup any wire load in OpenSTA. Maybe it has some default? | 16:25 |
| killjoy | ABC does not look like a timing analysis tool, so I would tend to believe opensta, who's output looks more like a timing analysis tool should. | 16:30 |
| killjoy | And if wireload is zero it is probably zero, but read the manual. | 16:31 |
| jonpry | I cannot make sense of the OpenSTA output. 0.00 0.00 ^ _108437_/CLK (sky130_fd_sc_hd__dfrtp_1) | 16:32 |
| jonpry | 5.82 5.82 ^ _108437_/Q (sky130_fd_sc_hd__dfrtp_1) | 16:32 |
| jonpry | Says Clk->Q on the DFF is 5.82ns. How can that be? | 16:32 |
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| killjoy | Ok, so you need to read that report and understand it, from top to bottom. | 16:33 |
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| killjoy | Your start is the rising edge of the clk, clock network delay is ideal so you have no load, and the times are probably in picoseconds through the path. | 16:34 |
| tnt | Not really sure what ^ and v mean but the rest is pretty clear. | 16:35 |
| tnt | PRetty sure the times are in ns. | 16:36 |
| killjoy | I also see no interconnect delays, just gate delays, so again, wireload is zero. AKA: you are not running an annotated timing sim. | 16:36 |
| jonpry | The liberty file says time units are ns. And I know from experience that the approximate speed of sky130 logic is in the 100ps range | 16:36 |
| killjoy | ns is a long time though. | 16:36 |
| tnt | heh, this is not a state-of-the art process ... | 16:37 |
| killjoy | tnt: If it takes 5ns to charge a pin on a gate, that's forever. | 16:37 |
| tnt | yeah | 16:38 |
| killjoy | Ok then. Last time I did STA signoff I was working at 28nm process node, so could be. | 16:39 |
| tnt | ps is just not believable. | 16:39 |
| killjoy | Ok if you say so. It's been a while since I did STA signoff so maybe I'm just rusty. | 16:40 |
| killjoy | tnt: The ^ and v are likely rising and falling edge indicators. | 16:40 |
| killjoy | So clk rises, Q rises, X rises, Y falls, etc. | 16:41 |
| tnt | Oh right yeah, asymettric delays, good call. | 16:41 |
| killjoy | Cell libraries have different characteristics for rise times and fall times. | 16:41 |
| killjoy | Gates are not perfectly symmetric. | 16:42 |
| killjoy | Well, IME anyway. | 16:42 |
| killjoy | This path is basically saying "it's way long dude, put in some pipeline stages or make it shorter." | 16:43 |
| tnt | Some things are a bit surprising to me in that report : (1) you have clkbuf and clkxxx cells in the path ... those are usually special for the clock tree and not meant for general purpose logic and shouldn't be inferred. (2) some cells seem to take a _very_ long time. (3) they are all the _1 variant like is the upsizing process didn't occur to compensate the gate size with the net fanout. | 16:43 |
| killjoy | I'm used to looking at primetime reports. There should be a number in this report that indicates the fanout on a pin. | 16:45 |
| killjoy | But I don't see it. | 16:45 |
| killjoy | Oh god, googling this stuff brings back so many memories... | 16:47 |
| jonpry | I agree with those observations. The yosys synthesis script can probably me modified to prevent it from using clock buffers. But it's still not clear to me why the Clk->Q thing happens. Even if I run the OpenSTA included examples. They are all like 2-3 gate circuits and for some examples it shows this huge CLK->Q and for other examples it shows as .2ns | 16:47 |
| killjoy | You don't worry about that clk->Q. | 16:49 |
| killjoy | You have to clock your flop for it to work, man. | 16:49 |
| killjoy | Else, nothing happens. | 16:49 |
| killjoy | This is from Parallax? | 16:51 |
| jonpry | The flop has maximum operating speed > 200mhz, in fact it can go ghz | 16:54 |
| killjoy | Good for you? | 16:55 |
| killjoy | It still has a propagation delay of 5.82ns apparently. | 16:55 |
| jonpry | But it doesn't | 16:55 |
| killjoy | Well then your configuration is wrong for your synthesis. | 16:56 |
| killjoy | AKA: you used the wrong flop. | 16:56 |
| killjoy | Because _THAT_ flop has a 5.82ns propagation delay from clk->Q. | 16:56 |
| tnt | jonpry: what process corner did you use ? | 16:57 |
| killjoy | And that's a good question. | 16:57 |
| jonpry | sky130 typical | 16:57 |
| killjoy | It's also the smallest drive flop (probably) in the library. | 16:57 |
| tnt | tt_025C_1v80 ? | 16:57 |
| killjoy | If I'm interpreting the nomenclature correctly. | 16:58 |
| killjoy | Holy crap this is a big node. | 16:58 |
| tnt | yes, _1 is the weakest output drive. | 16:58 |
| tnt | yeah, it's mixed 130/180 nm. | 16:58 |
| jonpry | sky130_fd_sc_hd__ff_n40C_1v76 | 16:58 |
| killjoy | 1v8 is huge to me. | 16:58 |
| tnt | I ask you what process corner you tell me "typical", then you pull out a "fast/fast" one ... | 16:59 |
| jonpry | Well, I got it wrong. the fast/fast is what the pastebin was generated on | 17:00 |
| killjoy | tnt: Is this a free library or something? | 17:00 |
| killjoy | nvm found it. | 17:00 |
| tnt | yeah, it's the skywater 130nm process that's freely available PDK | 17:00 |
| tnt | (hence why it's "old") | 17:01 |
| killjoy | I need to change my thinking, don't mind me. | 17:01 |
| killjoy | There's lots of old processes that get wide use, I'm just not used to them. | 17:01 |
| killjoy | When I was in this sphere, we were chasing the bleeding edge of what TSMC had to offer because I worked for PMC-Sierra back when it existed. | 17:02 |
| killjoy | It's been a while though so I should just be more accepting of the things I don't know. | 17:02 |
| tnt | But still, in that liberty file I don't see anything close to 5 ns clk->q. | 17:03 |
| jonpry | Maybe it is huge fanout. Does yosys know how to make tree's of buffers to drive large loads? | 17:04 |
| jonpry | Funny thing is that this design runs 100mhz in fpga | 17:04 |
| tnt | as I said, I'm already surprised all your gates are _1 | 17:05 |
| tnt | buffer / upsizing / ... are additional steps. | 17:06 |
| tnt | AFAIR the openlane custom ABC script does them. | 17:06 |
| killjoy | Yeah, we're pretty sure your synthesis script is screwy. | 17:07 |
| killjoy | It looks like it did a simple first-pass synthesis and nothing else frankly. | 17:08 |
| killjoy | As far as the ABC output, I wouldn't even look at that really. | 17:09 |
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