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| sf-slack | <torsten.reuschel> @fahrenkrog: 0x1F is the address of the configuration register, cf. last row of Table 5-23 of ug470. I was not able to pin down where the value is set, though, i.e. where 0x0b is written to this address. @tmichalak: Do you have any hints on where the value of the register may be written? | 14:57 |
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| sf-slack | <tmichalak> @torsten.reuschel so what I was actually thinking of doing is adding the appropriate entry to the configuration part just like here: https://github.com/SymbiFlow/prjxray/blob/master/lib/xilinx/configuration.cc#L313 only to the BSPI register (https://github.com/SymbiFlow/prjxray/blob/master/lib/include/prjxray/xilinx/configuration_register.h#L82) as it is clearly missing aka falls back to the defaults. The config spec | 15:25 |
| sf-slack | on page 122 states that the default value is 0xB which according to the opcodes on page 54 equals Fast Read x1 which is exactly what you observe. So you would have to change it to 0x6B for Quad Output Fast read I guess | 15:25 |
| sf-slack | <torsten.reuschel> @tmichalak: Thank you, configuration.cc#L313 was what we were looking for. @fahrenkrog: Are you able to edit configuration.cc accordingly and confirm faster boot up? | 15:33 |
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