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| sf-slack | <torsten.reuschel> @acomodi: You introduced `XRAY_IOI3_TILES` in https://github.com/SymbiFlow/prjxray/commit/5c829daa8ca2661a08505a6b0a286e4eba7f5d9d How do I populate type and coordinates, e.g. `LIOI3_X0Y9` , for a new part? | 02:34 |
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| sf-slack | <torsten.reuschel> @litghost @mkurc: Same result for fuzzer/005 after adjusting `XRAY_ROI_TILEGRID` to encompass the entire fabric of xc7k325t: orphan_int_column returns an empty list. All other tests of 005 complete without error. Here's the settings that I am using: https://github.com/unbtorsten/prjxray/blob/add_xc7k325t/settings/kintex7_325t.sh fuzzers 000, 001, 072, 075 pass without issue. Still waiting for results from 073 | 02:39 |
| sf-slack | and 074, however, these start up and seem to operate fine as well. Where could I go from here? | 02:39 |
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| sf-slack | <mkurc> @torsten.reuschel I'm not entirely sure why this orphan_int_column was needed for other fabric(s). Maybe it is simply not present in the one you are targeting? You may try disabling that. If the fuzzer completes without it at least you will have a partial tilegrid which is something to start with. | 08:34 |
| sf-slack | <acomodi> @torsten.reuschel the IOI3_TILES are handled here: https://github.com/SymbiFlow/prjxray/blob/60168e9b7e89956ce8a197f3cfdf6d4bc80926d3/fuzzers/005-tilegrid/generate_full.py#L499-L520. IIRC the tiles in the env variable were empirically discovered, possibly looking at the results of the intermediate IOI3 (https://github.com/SymbiFlow/prjxray/tree/master/fuzzers/005-tilegrid/ioi) fuzzer | 08:52 |
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| sf-slack | <fahrenkrog> @tmichalak Yes, it is strange, so I went (temporarily) the Vivado way and found this while generating an MCS file from th BIT file (messages in screenshots). Basically, it seems the bitfile is configured as an SPIx1 bitstream and not an SPIx4 bitstream, when generated by Symbiflow. That would suggest why your designs load in 1-2 secs and mine closer to 10. Is there a way to define that on when generating bitstreams? | 11:49 |
| sf-slack | <tmichalak> @fahrenkrog right, so this setting is in the Fpga Configuration part of the bitstream that is currently hardcoded and can't be modified at runtime by xcf7rames2bit. I will try to find the part of the code that is reponsible for this setting in the code. | 14:57 |
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| sf-slack | <torsten.reuschel> @tmichalak @fahrenkrog: Are you looking for this line? https://github.com/SymbiFlow/prjxray/blob/master/lib/include/prjxray/xilinx/xc7series/command.h#L35 documentation for this register can be found on Tables 5-23 and 5-41 of https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf | 16:42 |
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| sf-slack | <torsten.reuschel> @acomodi: From the output of fuzzer/005-tilegrid/ioi for artix7_50t, I don't see how this would justify the entries in https://github.com/SymbiFlow/prjxray/blob/master/settings/artix7_50t.sh#L22 In fact, the given entries are not even listed in the resulting segbits_tilegrid.tdb. I'll try to get away with not setting the environment variable in case of xc7k325t | 17:50 |
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