Sunday, 2021-10-10

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lkclVarun used the instructions from symbiflow-examples to install symbiflow, this was how he got the error (when using it to build libre-soc source)10:02
lkclhe's now successfully removed the (optimised) version of vtr10:02
lkcland replaced it with the (non-optimised) upstream version10:02
lkcland got the exact same error10:02
lkclhttp://lists.libre-soc.org/pipermail/libre-soc-dev/2021-October/003856.html10:02
tpbTitle: [Libre-soc-dev] LibreSOC Implementation on arty7 fpga dev boards. (at lists.libre-soc.org)10:02
sf-slack<gergo> @kgugala thanks for all your help, with this I managed to make an MMCM purely in HDL (no proprietary XML!)! Unfortunately I ended up hitting a failure of routing (https://github.com/SymbiFlow/vtr-verilog-to-routing/issues/570) but hopefully my repro repo is small enough that someone will be able to figure out why it fails.10:14
lkclgergo: it's totally cool, isn't it? :)10:16
sf-slack<gergo> but I did see the change in clock by blinking some LEDs!10:16
lkclgergo: have you run the circuit through a simulator such as verilator already?10:17
lkcl(or cocotb, which puts a python wrapper around the VPI - Verilog Procedural Interface)10:17
lkclcocotb is nice, it "manages" the whole process of building with either icarus-verilog, verilator, or GHDL, automatically for you10:18
lkclyou'd be able to check that the design doesn't have errors in it, and at least get you access to VCD/FST signal traces10:20
sf-slack<kgugala> you can try adding a bufg a the MMCM ouptut11:13
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