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| sf-slack | <cjearls> I have a question about the FPGA clock speed setting with a .xdc file with a Nexys4DDR. Can the "create_clock" command be used to create any clocks and automatically configure PLLs? For instance, is there a way to make it so that `create_clock -period 20 [get_ports {clock}]` could be used to have a 50 MHz clock instead of the default 100 MHz clock, or is this something that needs to be done manually? | 02:14 |
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| sf-slack | <kgugala> create _clock only informs the tools that there is a clock with certain frequency, so the tools can take this into account while placing/routing. It does not create a real clock - this has to be done in the design | 05:33 |
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