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| emilazy | mithro: so uh, any word from libera staff now that you got k-lined? :p | 18:53 |
| emilazy | (leenode decided to ban IRCCloud...) | 18:53 |
| mithro | emilazy: No word yet | 18:56 |
| mithro | Let me check my spam filter hasn't caught something... | 18:57 |
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| emilazy | fwiw I emailed them on May 27 about a group registration and they got back to me Jun 6 | 18:58 |
| emilazy | I already had a group registration on freenode though so maybe it was quicker for them to transfer | 18:58 |
| mithro | emilazy: Nope, nothing that I can see | 19:12 |
| mithro | Sent back on the 31st May | 19:13 |
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| tpb | <sf-slack> <josh.johnson.hire> Hello everyone! Hope this is the right channel. I would love to find a way to contribute to this project. I've got decent experience with FPGA design, but only recently finished my E.E. degree so I'm still inexperienced. I'm pretty good with Verilog and C, and am learning Python now. If anyone knows who I should contact to get involved, let me know! Thanks everyone. | 21:29 |
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