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| tpb | nick change by proteusguy to proteusguy-awk on freenode | 04:33 |
| jophish | even better, just drop the freenode channel... | 05:14 |
| yeti | ++ | 05:14 |
| yeti | meanwhile something like this may help: https://yeti.tilde.institute/brain/weechat.html#plonk- | 05:15 |
| tpb | Title: WeeChat (at yeti.tilde.institute) | 05:15 |
| jophish | hmm, I can toggle tpb's messages wholesale (in Element). Guess that'll have to do | 05:17 |
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| tpb | <sf-slack> <hadirkhan10> Hi guys, I have seen examples of PicoSoC on the symbiflow-examples github repository. I was thinking of adding the example of building Picofoxy. Any head start for this? Just need to open a PR for adding this support? | 11:14 |
| tpb | <sf-slack> <hadirkhan10> It'll be the first SoC based on Chisel to be included :) | 11:15 |
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| tpb | <sf-slack> <kgugala> @hadirkhan10 the whole eexamples repo is tested from the docs, so if you want to add sth you basically need to extend the docs with a guide how to build the example | 13:30 |
| tpb | <sf-slack> <kgugala> we use `tuttest` to extract code snippets from the documentation | 13:30 |
| tpb | <sf-slack> <kgugala> and simply run those snippets in CI | 13:31 |
| tpb | <sf-slack> <kgugala> I suppose you need to write some guide how to install all the stuff you need to build the CPU (Java, sbt etc.) | 13:31 |
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| tpb | <sf-slack> <hadirkhan10> Let's see how far I can go with this procedure ,:) | 14:21 |
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| tpb | <sf-slack> <vastarparaakshar> I just want to ask, does anyone here has post simulation running with arty-35 with modelsim? | 16:27 |
| tpb | <sf-slack> <vastarparaakshar> with symbiflow | 16:27 |
| tpb | <sf-slack> <acomodi> Hi @vastarparaakshar, I believe you meant post synthesis, but anyways, given that during synthesis the cells get tech-mapped to VPR-compatible cells, the synthesis output netlist cannot be used with xc7 simulation libraries. I think though that it should be doable to get the original netlist with fasm2bels and simulate that one | 16:31 |
| tpb | <sf-slack> <vastarparaakshar> https://symbiflow.readthedocs.io/en/latest/vtr-verilog-to-routing/doc/src/tutorials/timing_simulation/index.html | 16:36 |
| tpb | <tpb> Title: Post-Implementation Timing Simulation — SymbiFlow (at symbiflow.readthedocs.io) | 16:36 |
| tpb | <sf-slack> <vastarparaakshar> So you meant to say the primitives that needs to be supplied, can be generated using fasm2bels? | 16:38 |
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| tpb | <sf-slack> <nelson> @gatecat Thanks for the explanation. The reducing code path differences between families makes sense… | 18:19 |
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