Thursday, 2021-06-03

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mithroTesting?01:48
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mithroSaying random words...01:53
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tansellTesting?01:58
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tansellTesting?02:16
tansellThink probably time to give up for the night...02:22
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tansellI probably don't know when to quit....02:36
tansellThe Relay plugin doesn't like me apparently :-(02:39
tpb<mithro> Or maybe it does now?02:39
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tpb<cr1901_modern> Plugin seems to be working now?03:04
cr1901At least, seems to be03:06
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emilazyis this channel, uh, registered yet? :)06:52
lambda/cs info says no :)07:07
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tpb<sf-slack> <hadirkhan10> Hello guys, I am building an SoC generated from Chisel. I am using MMCM through clocking wizard in Vivado to create a clock of 8MHz. I want to build the buildstream through Symbiflow but the clocking wizard utilizes a module MMCME2_ADV which is Xilinx's closed IP. Any other way to use the PLL for my design and map it to the Arty A7 board?11:08
tpb<sf-slack> <kgugala> hi @hadirkhan10 MMCME2_ADV is not a closed IP. It is a primitive available i 7 series FPGAs. It is supported in Symbiflow - you can simply instantiate it in your design11:11
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tpb<sf-slack> <hadirkhan10> @kgugala I got an error. Something like `module definition for MMCME2_ADV not found` I will share the error when I'll re-run it12:02
tpb<sf-slack> <kgugala> you can always try replacing MMCME2_ADV with PLLE2_ADV12:08
tpb<sf-slack> <hadirkhan10> Oh.. let me see12:14
tpb<sf-slack> <hadirkhan10> @kgugala to be precise I used the clocking wizard to generate a clock using MMCM option. It created two files. 1) just a wrapper 2) filename: clk_wiz_0_clk_wiz.v instantiates the MMCME2_ADV When replacing the MMCME2_ADV module in the file PLLE2_ADV I am getting the following error: ERROR: Module `PLLE2_ADV' referenced in module `clk_wiz_0_clk_wiz' in cell `mmcm_adv_inst' does not have a port named 'CLKFBSTOPPED'.12:30
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tpb<sf-slack> <kgugala> PLLE does not have this port13:19
tpb<sf-slack> <kgugala> If you really want to use clk wizzard I believe you can tell it to use PLLE instead of MMCM13:20
tpb<sf-slack> <kgugala> I'd suggest instantiating those by hand13:20
tpb<sf-slack> <kgugala> those are not complicated and it's way easier to maitain the project if you do it mnually13:20
tpb<sf-slack> <kgugala> see https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf (page 70)13:21
tpb<tpb> <https://x0.no/4uwoj> (at www.xilinx.com)13:21
tpb<sf-slack> <kgugala> you can find there PLLE ports description (+ some info how this primitive works)13:22
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tpb<sf-slack> <hadirkhan10> @kgugala thanks, let me look into it :)13:50
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tpb<sf-slack> <vastarparaakshar> We are stuck at post-timing implementation simluation16:31
tpb<sf-slack> <vastarparaakshar> We almost got everything right, but we are having problem with primitives.v for tb.do16:31
tpb<sf-slack> <vastarparaakshar> so for primitives.v we need to manually find out blocks and add it on the file or we just need to attach some generated files already?16:32
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cr1901mithro: Did you put in a registration to Libera yet for this project?20:54
cr1901Asking b/c, well, no one has ops and the channel isn't registered yet20:54
emilazystarting to think it may be best to ping mithro over a non-IRC communications medium :p21:14
mithroI have sent the email21:14
cr1901emilazy: Nah, mithro's historically good w/ getting back to me. These are exceptional times21:17

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