Wednesday, 2022-06-22

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zx2c4shorne: oh thanks ill fix that re:virt11:18
zx2c4and yea i also tried the same with irqsaverestore in those places and found the same things11:18
shornezx2c4: I was reading the code a bit more (probably just forgot) but the on_each_cpu_mask framework already takes care of preempt_disable/enable and most of what my patch does11:35
shorneso really what my patch did doesnt do much at all11:35
shorneso somewhere else we are getting locked up11:36
shorneI'll try lockdep and other debug options to see if something comes out11:36
shorneI found one place (update_mmu_cache) where the or1k port calls on_each_cpu, but should just execute on the local cpu, so fixing that would be good11:37
shornethat fix still doesnt solve the lockups11:40
shornezx2c4: thanks for the virt patch probably that one is better for your needs11:51
zx2c4shorne: btw do you plan to do goldfish_tty in the virt machine like m68k does?11:58
shorneno, I was planning to continue with the 8250 serial, any reason to use goldfish?12:09
shorneno one replied to my patches to convert goldfish-rtc to configure it as big-endian12:10
shornezx2c4: why use goldfish_tty?12:10
zx2c4annoying nobody replied to that, hm12:10
zx2c4i dunno, i just noticed its what other things are using. it's a "virtualization tty"12:11
zx2c4dunno if that counts for much12:11
zx2c4seems to have an early serial mode12:11
shornethe current serial has early serial12:11
shorneif you run qemu with '-append earlycon' it works12:12
shorneI just added it your Makefile, it seems to work for me even with the current .config12:13
shorneI am not sure if '-append earlycon' works for all platforms though12:13
zx2c4huh12:30
zx2c4btw m68k (smp=1 platform) finishes over a minute faster than or1k NR_CPU=112:30
shorneinteresting, ill have to compare instructions12:31
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wxwisiasdfhello ?20:53
wxwisiasdfany1 here?20:53
shorne hello20:58
wxwisiasdfshorne: oh hello21:00
wxwisiasdfso uhm, i'm quite interested in OR1K i find it fascinating - in contrast to RISC-V which gets all the acclaim21:00
shornewxwisiasdf: thats good, risc-v is also nice, but or1k I feel has low barrier to entry21:02
wxwisiasdfreally? huh, neat21:02
shornefor example we just have one spec document, not 10s of extensions21:02
wxwisiasdfsorry for not knowing, but where can i find said document?21:03
shornehttp://openrisc.io/architecture <-- latest 1.4 version pdf is here21:03
tpbTitle: Architecture - OpenRISC (at openrisc.io)21:03
wxwisiasdfincredible, the vector extensions and stuff are out-of-the box right, not extensions like rv?21:04
shornewell, yes if the core implements it21:04
shornein openrisc there are a few instructions that are optional and so not implemented in every cpu21:05
wxwisiasdfoh,21:05
wxwisiasdflike which?21:05
shorneI can't recall I would have to search, we have or1200, mork1x and marocchino implementations21:06
shornewould need to look at verilog code21:06
wxwisiasdfah, well, for economical reasons i don't have the possibility of buying an fpga21:07
wxwisiasdfbut qemu should work right, right?21:07
shorneI have been doing mostly qemu for recent development...21:07
shorneqemu doesn't have the vector extensions yet, it would not be too hard to add21:09
wxwisiasdffair,21:09
shornewxwisiasdf: I need to head off21:15
shornezx2c4: I think these smp lockups may be qemu issues, the failures/deadlocks are always when running IPIs on cpus21:15
shornemy guess is the IPI hardware in qemu is not working right, i.e. if we get a timer and ipi at the same time, only the timer is run, then the ipi gets lost21:15
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