| *** tpb <[email protected]> has joined #openrisc | 00:00 | |
| shorne | zx2c4: ok, alsmost done adding the multi-way tlb support to the kernel (qemu is done, but cant test until I get both sides working) | 01:09 |
|---|---|---|
| shorne | kernel tlb flush logic updated to use multiple ways | 01:10 |
| shorne | now need to do the tlb miss handlers, which is all in aseembly, so it will take a bit of careful time | 01:10 |
| shorne | hope this helps with the lockups | 01:11 |
| shorne | this is the qemu patch: https://github.com/stffrdhrn/qemu/commits/or1k-virt-2 | 01:15 |
| shorne | tlb looksups now has a loop to check all set ways, I don't think it will impact performance too much | 01:16 |
| zx2c4 | Woah! | 08:58 |
| zx2c4 | I didnt realize that'd require kernel changes too, wow | 08:58 |
| zx2c4 | Will this see its way into an FPGA eventually | 08:58 |
| shorne | its already in the fpga | 10:27 |
| shorne | its just the kernel is not using it | 10:27 |
| shorne | zx2c4: the kernel hard codes the way select to 0 alreays, so it limits the tlb size to 128 entries even though we have support for 512 in hardware | 10:28 |
| shorne | qemu also was limited to 1 way, probably because the kernel doesn't support more | 10:29 |
| zx2c4 | Oh cool | 10:50 |
| shorne | ok, its working but performance doesn't seem so great | 13:01 |
| shorne | https://github.com/stffrdhrn/linux/commits/or1k-virt | 13:05 |
| shorne | zx2c4: maybe you can try it out, ill see if I can tune the performance more | 13:05 |
| shorne | currently TLB way selection strategy is just using more address bits, I can change to use an LRU method in the kernel, it might help, but it will be a bit tricky to access the LRU info from the assembly code | 13:07 |
| shorne | ah.. still getting rcu stalls, boot time is a bit faster | 13:14 |
| shorne | sometimes, need a lot more debugging | 13:15 |
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