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| benjaminh-13 | Hello, | 14:04 |
|---|---|---|
| benjaminh-13 | I'm trying to implement a NaxRiscv-based SoC on FPGA but synthesis fails, as when instantiating the NaxRiscv, the SoC's top level module tries to connect to port which do not exist. Precisely, I'm trying to add a JTAG debug module within the Nax, which thus exposes I/O ports in the Nax's top level, but for some reason, when integrating the Nax in | 14:04 |
| benjaminh-13 | the SoC's top level, Litex seems to change the name of the JTAG ports to some other name, which thus causes an error during synthesis. | 14:04 |
| benjaminh-13 | Therefore, I was wondering where in the Litex flow (and in its code base) are ports from a module retrieved ? I think figuring out how does Litex recover the port name of an instance would help me save this issue. | 14:04 |
| benjaminh-13 | Thanks, | 14:04 |
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