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| sajattack | when I increase this variable (to 16MB bar size) it just breaks litepcie_util info and dmesg also reports ffffffffffffffffffffffffffffff for the device name or whatever. The bar size reported by sysfs remains 1MB, and the device is unusable. For a while I thought something was wrong with my programming procedure but it turns out that once I lower it back to 1MB everything's happy | 07:06 |
|---|---|---|
| sajattack | https://paste.sr.ht/~sajattack/b2fe93aec9df51b0b286c432798c26c95fb6a491 | 07:09 |
| tpb | Title: b2fe93a — paste.sr.ht (at paste.sr.ht) | 07:09 |
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| sajattack | sorry if it seems like I'm complaining a lot, just trying to get back up to speed and hitting a few roadblocks | 07:13 |
| sajattack | is this hardcoded 1 the reason? https://github.com/enjoy-digital/litepcie/blob/be0abebc972cea17644e2415e0eb1a5db71353fc/litepcie/phy/s7pciephy.py#L487 | 07:49 |
| sajattack | yes, yes it is | 09:26 |
| sajattack | how do I define what the bar maps to? | 09:28 |
| tnt | It connects to the global "SoC" address space basically. | 09:31 |
| sajattack | at what address offset? | 09:33 |
| tnt | I use something like self.bus.add_slave(name="radio", slave=mybus, region=SoCRegion(origin=0xf0040000, size=0x40000, cached=False)) to connect a custom wishbone peripheral to part of it. | 09:33 |
| tnt | I think it starts at 0xf0000000 | 09:33 |
| sajattack | thanks | 09:34 |
| sajattack | my goal right now is to display a single colour other than black or white on my framebuffer. time to figure out wishbone | 09:48 |
| sajattack | TODO D: https://github.com/enjoy-digital/litex/wiki/Wishbone-Bus#wishbone-bus-example-in-litex-socs | 09:49 |
| sajattack | thankfully found this https://github.com/enjoy-digital/litex/issues/1368 | 09:52 |
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