Tuesday, 2025-01-14

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ksczif anyone happens to see this - I could use some help tracking down this issue: https://github.com/enjoy-digital/litex/issues/215717:25
flygoatkscz: Commented on JTAG issue17:59
flygoatIn the worst case, if you can't get JTAG working on any core, you can still trace bus activities to see what's going on18:01
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ksczThank you for taking a look!18:31
ksczThe main frustration is that I can't use JTAG on the real hardware because I don't have any available pins to map the JTAG onto18:32
ksczWell, interestingly, the issue does not appear to repro in vexriscv_smp, but I'm getting a bunch of different issues with that core18:51
kscznevermind - the issue repros in vexriscv_smp in the FPGA, but not in the simulator?20:28
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