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kscz | if anyone happens to see this - I could use some help tracking down this issue: https://github.com/enjoy-digital/litex/issues/2157 | 17:25 |
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flygoat | kscz: Commented on JTAG issue | 17:59 |
flygoat | In the worst case, if you can't get JTAG working on any core, you can still trace bus activities to see what's going on | 18:01 |
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kscz | Thank you for taking a look! | 18:31 |
kscz | The main frustration is that I can't use JTAG on the real hardware because I don't have any available pins to map the JTAG onto | 18:32 |
kscz | Well, interestingly, the issue does not appear to repro in vexriscv_smp, but I'm getting a bunch of different issues with that core | 18:51 |
kscz | nevermind - the issue repros in vexriscv_smp in the FPGA, but not in the simulator? | 20:28 |
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