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| jersey99 | Hello hello, I have a quick question: Anybody instantiated the "Hybrid" LiteethMAC with eth_mtu set to 9k on a Xilinx FPGA? If so how did the synthesis go? I seem to hit a limit where Vivado tries to convert the SRAM into a DRAM and fails. | 18:53 |
|---|---|---|
| jersey99 | WARNING: [Synth 8-4767] Trying to implement RAM 'mem_2_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons. | 19:37 |
| jersey99 | Reason is one or more of the following : | 19:37 |
| jersey99 | 1: No valid read/write found for RAM. | 19:37 |
| jersey99 | ERROR: [Synth 8-3391] Unable to infer a block/distributed RAM for 'mem_2_reg' because the memory pattern used is not supported. Failed to dissolve the memory into bits because the number of bits (72000) is too large. Use 'set_param synth.elaboration.rodinMoreOptions {rt::set_parameter dissolveMemorySizeLimit 72000}' to allow the memory to be | 19:37 |
| jersey99 | dissolved into individual bits | 19:37 |
| jersey99 | Adding the FullMemoryWE doesn't seem to help the situation | 19:37 |
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