Wednesday, 2024-07-10

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Guest78Hello all, I am trying to use LiteX to build a SoC on a Fomu board (Lattice iCE40 UP5K), but I am getting an error when I set --cpu-type to None:11:35
Guest78$ ./lattice_ice40up5k_evn.py --cpu-type None --build11:35
Guest78...11:35
Guest78ERROR:SoCBusHandler:Region overlap between sram and csr:11:35
Guest78ERROR:SoCBusHandler:Origin: 0x00000000, Size: 0x00020000, Mode:  RW, Cached:  True, Linker: False11:35
Guest78ERROR:SoCBusHandler:Origin: 0x00000000, Size: 0x00010000, Mode:  RW, Cached: False, Linker: False11:35
Guest78$11:35
Guest78Has anybody seen this before?11:35
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