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| joseng | I'm not very experienced at interpreting the timing reports. Posted them here: https://gist.github.com/Wardstein/44369da6d5bc1b357a765e72eec949d0 As I understand them, 40 signals from the bankmaschine of the DDR interface in the "sys" clockdomain and CSR signals to and from the video frame buffer (cd_sys to cd_hdmi and back) | 11:20 |
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