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| somlo | I just updated https://github.com/litex-hub/linux-on-litex-rocket with instructions on how to work with "contemporary" (opensbi) based firmware | 20:21 |
|---|---|---|
| gurki | how does this compare to https://github.com/litex-hub/linux-on-litex-vexriscv ? | 20:34 |
| gurki | im aware these are different cores, but i am curious since i never looked at the rocket version | 20:34 |
| gurki | (disclaimer: i am not involved with the latter) | 20:34 |
| somlo | funny, I never got around to using vexriscv :) But AFAICT, vexriscv is 32-bit, and I needed a rv64gc compliant cpu to be able to run a "real distro" (e.g., Fedora) | 20:51 |
| sorear | if you were using bbl you would only need a rv64imac cpu because it supports FP emulation, how much does losing that feature hurt you? | 21:31 |
| somlo | sorear: not that much, TBH -- emulating the FPU was always too slow and awkward to boot Fedora (I mean, this thing isn't winning any speed competitions at 50MHz as it is :D ) | 21:43 |
| somlo | my entire "shtick" was to prove that it's practically possible to build a computer that can run a modern distro and use the included packages (yosys/nextpnr) to rebuild its own underlying bitstream (i.e., "self-hosting") | 21:45 |
| somlo | there's 32-bit cores for anythng more lightweight than that, so no point chasing after that "mindshare" :) | 21:46 |
| sorear | I'm surprised that the FPU emulation overhead on linux/systemd (which I assumed were mostly integer code) is worse than the clock rate and area hit from adding a FPU to rocket | 21:47 |
| sorear | I vaguely recall ca. 2016 nobody touching the rocket FPU for FPGA use because it impacted timing too much | 21:47 |
| sorear | (typically 100MHz, but that was on 7-series with vendor tools and your 50MHz number is probably for ecp5/yosys/nextpnr?) | 21:48 |
| somlo | it passes timing at 50MHz on ecp5 and the lower speedgrade artix7 chips (nexys ddr and video); I can get 75 MHz on a higher speedgrade artix7 (acorn board), and 100MHz on a kintex (genesys2) | 21:49 |
| somlo | but I don't much care about the xilinx side of things ATM (not until I can use yosys/nextpnr reliably to build the bitstream, circling back to the self-hosting angle) | 21:50 |
| sorear | there's an untapped market for "area/timing optimized multicycle FPU for people who just want sw compatibility"; NOEL-V has one but I have no real sense of how it performs | 21:51 |
| sorear | (noel-v is underappreciated in general, i think it's the only dual-issue open hardware design that isn't somebody's thesis project that they have no incentive to revisit) | 21:53 |
| somlo | fun times -- I'm somewhat limited by $DAYJOB in how much time I can dedicate to this... I'd like to dig into the xilinx version of nextpnr, figure out what it can do right now, what it would need to be out of "alpha/beta" (apologies to gatecat if my knowledge on that is out of date :D ) | 21:53 |
| sorear | if you find out let me know | 21:53 |
| somlo | I mean, I had the opensbi stuff for litex/rocket working since late 2022, only got around to updating github *now* :( | 21:55 |
| somlo | so I'll definitely let you know, it just might take a while :D | 21:56 |
| sorear | was that a "yes" on "does enabling the FPU on rocket with ecp5/yosys/nextpnr have no effect on the maximum frequency which can achieve timing closure?"? | 21:58 |
| somlo | haven't tried building a fpu-less rocket in a while (3 years or so); back then, on ecp5 and low speed-grade artix, it took me down to 50MHz from 70 or 75, iirc | 22:04 |
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