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hve | clock in Litex are confusing. Anyone know how to get the current clk Signal from within a litex module? | 13:37 |
---|---|---|
tnt | ClockSignal() | 13:38 |
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hve | Is this the same as "self.cd_sys.clk" ?? | 13:42 |
tnt | I think so. | 13:42 |
hve | I will try, tnx | 13:43 |
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hve | One more maybe: self.specials += Instance("pwm",p_WIDTH=width,... Instance("pwm", ... Is not a migen value | 14:27 |
hve | I have added the verilog file using add_source with a "module pwm" | 14:28 |
hve | Stupid mistake... fixed.. | 14:56 |
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