Friday, 2023-08-18

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MoeIcenowy_florent_: BTW I tried to tweak when dqs_re to be asserted, and the read leveling result seems better02:03
MoeIcenowywell it still doesn't pass read leveling...02:06
MoeIcenowytrying to deal with Python slicing is weird02:30
MoeIcenowyit behavior is so different to Verilog's02:30
MoeIcenowy_florent_: BTW on ECP5 is a high sys_clk needed for DDR to work ?02:44
MoeIcenowyI start to doubt 252MT/s is too slow for DDR302:45
MoeIcenowy(but the timing of GW2A is quite bad ...02:45
MoeIcenowyeven GW5A isn't something good02:45
MoeIcenowywell the JEDEC minimum is tCK = 3.3ns (300MHz clk) ...03:10
MoeIcenowythinking about migrating gw2ddrphy to 1:4 instead of 1:203:42
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_florent_MoeIcenowy: On ECP5 most of the targets are using 75MHz with DDR3 (so DDR 300) but it’s working fine at l’Eastwood down to   50MHz. trabucayre started adding 1:4 support so it could be worth exchanging together.05:48
MoeIcenowy_florent_: I did a quick try for 1:4 and then quick fail :-(06:25
MoeIcenowy300MT/s is also out of JEDEC spec (the JEDEC spec specifies at least 300MHz CK)06:26
MoeIcenowyBTW what's the meaning of "bus errors" of the DRAM controller?10:17
MoeIcenowywhat does it mean when the bus error is now 0 but data error still exist?10:18
MoeIcenowyand for the read_latency of phy_settings, is it just used for a hint?10:19
MoeIcenowyBTW I start to doubt that the latency of the read codepath on GW2 is kinda like 9.5 sys_clks10:26
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MoeIcenowyor 10.510:30
MoeIcenowybtw what's the difference between BitSlip currently used by ECP5/GW2 with the one in common?11:00
MoeIcenowyokay the common BitSlip reduces one cycle of delay11:04
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josuah_florent_: you can ignore most pull requests from me if you look at this issue which summarizes everything: https://github.com/litex-hub/zephyr-on-litex-vexriscv/issues/1418:15
_florent_@josuah: thanks19:46
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