Sunday, 2023-08-06

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nanoric[m]Hello, I'm new to FPGA. Am I free to ask questions about FPGA here?09:14
sensillenanoric[m]: i'm not the owner of this channel but i'd say it is quiet enough that you can. there's also ##fpga which is just general fpga talk with regular newbie questions09:31
nanoric[m]Thanks!09:44
nanoric[m]An fpga question:... (full message at <https://catircservices.org/_matrix/media/v3/download/catircservices.org/mbrJrDYBhZWFpUIvLBHkdWfB>)09:48
sensillenanoric[m]: have you read http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf?09:55
sensillerelevant here maybe up to page 1009:55
sensille(and it is very inconvenient to have to click on a link to see your question, i'm on the irc side)09:56
nanoric[m]sensille: Thank you for your recommand!09:56
sensillemy question would be, how do you know it is many clocks later?09:57
nanoric[m]Because I can wait many clocks later to read it. Read operation is not eager.09:58
nanoric[m]For example, I have a single to control the write from clock A, and another signal to control the read from clock B. The two signals are far apart in time.10:02
nanoric[m]* in time(eg, 10 or more clocks).10:03
sensillenanoric[m]: it should work (3 cycles should be plenty). the document might offer more solutions10:28
sensille5.6.1 resembles your solution10:38
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