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| jevinskie[m] | [gurki](<https://matrix.to/#/@gurki:libera.chat>) here is questa support but I think it’s broken against upstream since the GenericPlatform rework or whatever that was https://github.com/jevinskie/litex/blob/jev/usbstream-usbbone/main/litex/build/sim/questa.py | 03:21 |
|---|---|---|
| tpb | Title: You're invited to talk on Matrix (at matrix.to) | 03:21 |
| jevinskie[m] | iverilog is in there too | 03:22 |
| jevinskie[m] | And this is at least part of the work that exposes LiteX sim modules as VPI https://github.com/jevinskie/litex/blob/jev/usbstream-usbbone/main/litex/build/sim/vpi.py | 03:26 |
| jevinskie[m] | And the c++ portion https://github.com/jevinskie/litex/blob/jev/usbstream-usbbone/main/litex/build/sim/core/vpi.cpp | 03:28 |
| jevinskie[m] | I’m pretty sure you need a patch to get iverilog support working since I don’t think it follows the VPI spec correctly but I got distracted and never resolved this PR https://github.com/steveicarus/iverilog/pull/740 | 03:50 |
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