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| sensille | python again ... now I ran into https://github.com/enjoy-digital/litex/issues/1716 | 06:25 |
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| sensille | _florent_: liteeth and block ram again ... do you think it reasonable/feasible to block CPU reads to the tx buffers as long as the core transmits? | 10:10 |
| sensille | reducing the number of read ports to one would help my project significantly | 10:10 |
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| sensille | even better, i don't think i have to read back the txbuf at all | 12:00 |
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| tich | Good Day How do I generate Verilog code from a LiteX defined board | 13:45 |
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