*** tpb <[email protected]> has joined #litex | 00:00 | |
*** Degi_ <[email protected]> has joined #litex | 00:32 | |
*** Degi <[email protected]> has quit IRC (Ping timeout: 268 seconds) | 00:33 | |
*** Degi_ is now known as Degi | 00:33 | |
*** Emantor <[email protected]> has quit IRC (Quit: ZNC - http://znc.in) | 01:20 | |
*** Emantor <[email protected]> has joined #litex | 01:22 | |
*** Hammdist <[email protected]> has joined #litex | 01:25 | |
Hammdist | ok I have enabled "bist" and got the read speed 461 MiB/sec, which seems pretty decent | 01:26 |
---|---|---|
*** peepsalot <peepsalot!~peepsalot@openscad/peepsalot> has quit IRC (Read error: Connection reset by peer) | 01:33 | |
*** peepsalot <peepsalot!~peepsalot@openscad/peepsalot> has joined #litex | 01:35 | |
Hammdist | are native ports pipelined? in general, is there any documentation on how to interact with a native port (apart from reading the python code)? | 01:48 |
Hammdist | I see by default I get a 128-bit bus, but there are separate valid/ready on cmd and on wdata and on rdata ... looks complicated | 01:53 |
*** Flea86 <Flea86!~maomao@user/Flea86> has quit IRC (Read error: Connection reset by peer) | 02:28 | |
*** Flea86 <Flea86!~maomao@user/Flea86> has joined #litex | 02:41 | |
bjonnh[m] | I'm preparing a class for our local hackerspace on FPGAs and half of it is based on LiteX | 02:49 |
bjonnh[m] | I'm trying to prepare instructions for windows users, and I can't get the colorlight-i5 board to compile properly (works on Linux): http://paste.alacon.org/47741 | 02:50 |
tpb | Title: Paste à la con (at paste.alacon.org) | 02:50 |
bjonnh[m] | a simple example with just the litescope works | 02:51 |
Hammdist | found some partial answers to my question here: https://freenode.irclog.whitequark.org/litex/2020-05-14 | 03:07 |
tpb | Title: #litex on 2020-05-14 — irc logs at whitequark.org (at freenode.irclog.whitequark.org) | 03:07 |
bjonnh[m] | https://bjonnh.github.io/fpga_class_psone/requirements/windows/index.html | 03:24 |
tpb | Title: Windows setup :: PS1 FPGA Class (at bjonnh.github.io) | 03:24 |
bjonnh[m] | That's what I have for the windows setup | 03:24 |
*** so-offish1 <so-offish1!~so-offish@2610:148:610:2b11::10> has quit IRC (Quit: Leaving) | 06:06 | |
*** TMM_ <[email protected]> has quit IRC (Quit: https://quassel-irc.org - Chat comfortably. Anywhere.) | 10:50 | |
*** TMM_ <[email protected]> has joined #litex | 10:51 | |
*** Hammdist <[email protected]> has quit IRC (Ping timeout: 245 seconds) | 14:07 | |
SpaceCoaster | bjonnh[m]: I know it isn’t a good solution but commenting out one or both of the add_period-constraint lines for eth_clocks:rx in platforms/colorlight_i5.py worked for me on a Mac. | 15:03 |
*** Hammdist <[email protected]> has joined #litex | 15:06 | |
bjonnh[m] | thanks. this is weird there would be such a diff between platforms | 15:18 |
Hammdist | if sent commands on multiple ports, and those commands are largely bulk operations (read/write x, x+1, x+2, ...), does litedram interleave them in a reasonable way when sending them to the dram? by reasonable I mean performance should not drop greatly from interleaving | 15:33 |
bjonnh[m] | <SpaceCoaster> "bjonnh🥬: I know it isn’t a..." <- did you see any impact on the ethernet performance or behavior? | 15:37 |
*** Hammdist <[email protected]> has quit IRC (Quit: Client closed) | 16:45 | |
*** Hammdist <[email protected]> has joined #litex | 16:46 | |
bjonnh[m] | Curiously this function is not called at all on Linux | 16:57 |
bjonnh[m] | so I think that's a bug in the argument parsing | 16:57 |
bjonnh[m] | looks like on linux it doesn't go inside generic_toolchain at all | 17:01 |
*** dark_star_1 <[email protected]> has quit IRC (Ping timeout: 268 seconds) | 17:43 | |
bjonnh[m] | Also this bug still exists: https://github.com/YosysHQ/oss-cad-suite-build/issues/42 | 17:51 |
bjonnh[m] | Looks like trying a fresh install of OSS-cad and installing Litex in it doesn't work :( | 18:05 |
bjonnh[m] | (on Linux) | 18:05 |
bjonnh[m] | It does the install, I see all the modules in the site-packages of OSS-cad, but I get | 18:06 |
bjonnh[m] | python3 -m litex | 18:07 |
bjonnh[m] | /home/foo/oss-cad-suite/bin/tabbypy3: No module named litex | 18:07 |
*** cr1901 <cr1901!~cr1901@2601:8d:8600:911:4859:6504:4f22:af6f> has quit IRC (Remote host closed the connection) | 18:09 | |
bjonnh[m] | That's the instructions I'm trying to make (that used to work a couple of weeks back): https://bjonnh.github.io/fpga_class_psone/requirements/linux/index.html | 18:18 |
tpb | Title: Linux setup (recommended) :: PS1 FPGA Class (at bjonnh.github.io) | 18:18 |
bjonnh[m] | That seem to work on Ubuntu, but not Fedora... | 18:19 |
bjonnh[m] | Hmm ok false alert that seem to have been some environment pollution | 18:23 |
bjonnh[m] | (I would still appreciate if someones that knows these things could have a look at those instructions and see if they could be improved) | 18:23 |
bjonnh[m] | I think that oss-cad is using a mixture of my local python and the oss-cad one, that's what fails... | 18:25 |
bjonnh[m] | http://paste.alacon.org/47742 | 18:28 |
tpb | Title: Paste à la con (at paste.alacon.org) | 18:28 |
bjonnh[m] | I think that's where all the issues stem from, litex when installing is using 3.11 (from my local system) despite me telling it to use the oss-cad environment | 18:29 |
bjonnh[m] | I tried all that on a Ubuntu docker with no python installed and all works well. Except that now I get the same error as I did on windows ( AttributeError: 'NoneType' object has no attribute 'name_override') | 18:35 |
bjonnh[m] | https://github.com/enjoy-digital/litex/commit/fb0c9e846d72fc4fe99ca329cc84a8d2537d3d8d | 18:37 |
bjonnh[m] | That's the commit that likely broke all that | 18:37 |
bjonnh[m] | https://github.com/enjoy-digital/litex/issues/1696 | 18:42 |
bjonnh[m] | SpaceCoaster: ^^ just going back to before those changes solves the issue | 18:46 |
*** TMM_ <[email protected]> has quit IRC (Quit: https://quassel-irc.org - Chat comfortably. Anywhere.) | 19:31 | |
*** TMM_ <[email protected]> has joined #litex | 19:32 | |
*** cr1901 <cr1901!~cr1901@2601:8d:8600:911:90af:892b:466b:71a7> has joined #litex | 20:07 | |
SpaceCoaster | bjonnh[m]: good one! | 20:10 |
*** zjason`` <zjason``[email protected]> has joined #litex | 20:16 | |
*** zjason` <zjason`[email protected]> has quit IRC (Ping timeout: 240 seconds) | 20:18 | |
*** xgpt <xgpt!sid596957@user/xgpt> has quit IRC () | 20:33 | |
*** dark_star_1 <[email protected]> has joined #litex | 23:22 |
Generated by irclog2html.py 2.17.2 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!