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| sajattack[m] | it looks like florent is potentially trying to run SMB on my oscilloscope which I'm all for. | 00:25 |
|---|---|---|
| sajattack[m] | (extrapolating a bit) | 00:25 |
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| _florent_ | sajattack[m]: yes, I'm trying to explore a things a bit to see the possibilities and help Hans on MiSTeX for some features | 07:09 |
| sajattack[m] | Nice | 07:10 |
| _florent_ | sajattack[m]: it seems the different project could benefit from it: MiSTeR stuck with the De10-Nano, code that is not really portable on Xilinx or open-source toolchains, etc... and this could require adding some interesting features to LiteX | 07:12 |
| sajattack[m] | Yeah | 07:12 |
| _florent_ | sajattack[m]: One thing I'm also interesting to see is if we can emulate the SDRAM interface with LiteDRAM (and DDR3/DDR4) and a specific frontend | 07:13 |
| _florent_ | sajattack[m]: if so, we could probably run the cores with only a DDR3, which could be another simplification of the hardware | 07:14 |
| sajattack[m] | Sounds difficult | 07:14 |
| _florent_ | sajattack[m]: on paper, this seems possible. | 07:15 |
| sajattack[m] | The cartridges and such need very low latency random access | 07:15 |
| sajattack[m] | (simulated cartridges) | 07:16 |
| _florent_ | indeed, but if we can emulate the SDRAM timings, it would be fine | 07:17 |
| _florent_ | if you are interested to integrate the change you did in LiteX-Boards, feel free to create a PR for it. | 07:18 |
| _florent_ | will probably hack https://github.com/MiSTer-devel/MemTest_MiSTer to check feasibility | 07:22 |
| tnt | One annoying thing is that every core uses a different controller :/ | 08:05 |
| tnt | They are often derived from one another but they've been tweaked sometimes in subtle ways to fit whatever they were trying to emulate. | 08:06 |
| _florent_ | arf, this will not simplify things... | 08:12 |
| _florent_ | In fact to avoid touching too much MiSTeR internals (and keep these kind of tweaks) I was thinking about emulating the SDRAM directly on SDRAM pins (not on internal SDRAM interface). This way the controller used by the core would still be there. But we'll probably have to have much margin on DDR3 timings. | 08:14 |
| gatecat | this seems pretty tricky, because the basic access latency of DDR3/4 afaik isn't that much faster than SDRAM, so you don't have much margin for PHY etc | 09:35 |
| _florent_ | gatecat: looking at the numbers, this is indeed probably too ambitious at the SDRAM interface level: 22.5ns for a SDRAM @ 133MT/S, 15.00 for a DDR3 @ 800MT/S. | 10:08 |
| tnt | What freq do the cores run the SDRAM at ? I'd actually expect a lot of them to be quite a bit slower than 133MHz. | 10:12 |
| _florent_ | tnt: I also expect that for most of the cores. I'll probably study the requirements for the different cores | 10:24 |
| _florent_ | this could be worth creating a script to extract the SDRAM controller core and configuration for the different core and then see the freq and if the controller has been tweaked. | 10:26 |
| _florent_ | this could already provide a good idea of what we could run with a DDR3 doing the emulation | 10:26 |
| _florent_ | doing the emulation at the user interface of the SDRAM core will give more margin, but if some very specific timings are required due to a tweaked controller, it can easily become a nightmare | 10:28 |
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