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| _florent_ | gruetzkopf: Here is the Qsys file I was using: https://gist.github.com/enjoy-digital/7334385089436f555a95b5edda92b6b5 | 09:33 |
|---|---|---|
| gruetzkopf | Thank you! | 09:34 |
| _florent_ | gruetzkopf: The C5 port was a quick proof of concept I did for the LimeSDR QPCIe board 4 year ago on their request, but I haven't put more efforts into it after since they didn't seem interested to push this much further. | 09:36 |
| _florent_ | gruetzkopf: I tried to maintained the C5 Phy while doing changes to the other PHY, but the changes were not tested on hardware. | 09:37 |
| _florent_ | gruetzkopf: I still have some hardware to test this if required, so if you have trouble, I could try to help | 09:37 |
| gruetzkopf | Okay, that explains the rather limited docs/examples on this case, I'll see if I can get it up and running on S5GS (board with which are still plentiful for sub-100€) - I'll see what happens, thanks for the offer! | 09:37 |
| _florent_ | gruetzkopf: The format on the Avalon-ST are standard TLP and IIRC I just had to convert Avalon-ST to LiteX Streams | 09:38 |
| _florent_ | gruetzkopf: so mostly latency adaptations on the ready signal: https://github.com/enjoy-digital/litex/blob/master/litex/soc/interconnect/avalon.py#L15-L20 | 09:39 |
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