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| gurki | i am a bit confused how i would add a custom blackbox instruction plugin to vexriscv | 20:03 |
|---|---|---|
| gurki | https://github.com/SpinalHDL/VexRiscv#add-a-custom-instruction-to-the-cpu-via-the-plugin-system is quite informative regarding "how do i add a custom instruction at all", https://spinalhdl.github.io/SpinalDoc-RTD/dev/SpinalHDL/Structuring/blackbox.html tells me that spinalhdl (which - if i read correctly vexriscv uses) should be capable of this | 20:04 |
| tpb | Title: Instantiate VHDL and Verilog IP — SpinalHDL documentation (at spinalhdl.github.io) | 20:04 |
| gurki | but how would i actually do this? | 20:04 |
| gurki | bonus points if i can simulate the entire core in such a way that i can feed c code implementing this boxes behaviour to the simulator | 20:04 |
| gurki | this is a quite ... complex ... mixed signal core so i cannot provide an actual implementation for spinalhdl to convert to hdl | 20:06 |
| gurki | im not set on vexriscv per se, but i liked the plugin system | 20:07 |
| gurki | (i hope this is topical, i wasnt quite sure) | 20:08 |
| gurki | i do have a possible workaround for the simulation part using spike, but having everything nicely integrated is obv nicer | 20:09 |
| tpw_rules | do you want to do all this through litex? | 20:09 |
| tpw_rules | a bit confused about the part you are stuck at. doing it through litex? or hooking up a custom instruction that is not primarily based on spinalhdl? | 20:09 |
| gurki | my main focus is "how do i properly integrate a mixed signal core into vexriscv", i assumed that the reasonable way to do so is by using a custom instruction which i hand over as a blackbox | 20:11 |
| gurki | litex might be part of the solution | 20:11 |
| tpw_rules | why would it be an instruction and not an mmio peripheral? | 20:11 |
| gurki | is that wise? what this core does is (example, not what its actually doing) perform aes on a large chunk of data (ideally handed over via a memory adress) and return some result; but it would be nice to be able to just do "aes()" using an asm intrinsic from plain c | 20:14 |
| tpw_rules | and that can't be a store instruction into a peripheral? | 20:14 |
| gurki | i am looking for good ideas, thats why i asked. maybe your approach -is- better | 20:15 |
| tpw_rules | it seems a bit silly to just stall the core for a bunch of cycles to crunch on some data. i would heavily encourage an mmio approach i think | 20:15 |
| tpw_rules | that's not very RISC :P | 20:15 |
| tpw_rules | a mungeBlock you call in a loop maybe | 20:16 |
| tpw_rules | or swapStatus. i don't know much at all about the vexriscv plugin system though. just the litex guts | 20:17 |
| tpw_rules | they do have an iterative multiplication example which would be interesting to look at | 20:18 |
| gurki | i was just about to ask for an example to look at :3 | 20:18 |
| tpw_rules | (for a plugin) | 20:19 |
| tpw_rules | i don't think vexriscv conceptualizes mmio much. that is where you would step out to an SoC builder like litex | 20:19 |
| gurki | how much additional pain do i need to expect for setting up a simulation and getting synthesizable hdl? | 20:19 |
| gurki | (obv "not much" for sb who is already familiar ...) | 20:19 |
| tpw_rules | i don't know. that stuff using vexriscv through litex is very easy even for a noob. but it's pretty abstracte | 20:20 |
| tpw_rules | d | 20:20 |
| gurki | do i - at some point - get an interface to shove random c to the/a simulator? | 20:21 |
| gurki | it is probably using verilator, so i could do crappy function pointer yada, but id rather not | 20:21 |
| tpw_rules | it does use verilator somehow. i don't know the details about that. i'm not a heavy litex user | 20:22 |
| tpw_rules | but litex's wrapper around vexriscv is pretty simple. it just dumps specific verilog to disk at compile time of the vexriscv litex plugin and then reads those later | 20:23 |
| tpw_rules | so if you are more comfortable in verilog and want to put the things together yourself you can just use vexriscv's scala generators yourself | 20:23 |
| tpw_rules | someone else might be able to weigh in better on actually interfacing with simulation | 20:25 |
| gurki | well i will have to touch the verilog for the synthesis part, so its handy that i can do whatever to it and still verify the results | 20:25 |
| gurki | im still not sure whether i will ever have a verilog simulation model for that core since its. uh. "complicated" to do | 20:26 |
| gurki | characterizing larger mixed signal cores isnt exactly fun | 20:26 |
| tpw_rules | how do you plan to synthesize it | 20:26 |
| gurki | hence the need for "can i just plug in the c simulation model" | 20:26 |
| gurki | dc_shell to asic | 20:26 |
| gurki | it will happily take blackboxes | 20:27 |
| gurki | i will need to provide _some_ timing information, but that is yet another beast to deal with | 20:27 |
| tpw_rules | ah so you are not targeting an FPGA. that's what you mean by mixed signal, real analog. i sort of thought you meant like DSP | 20:27 |
| gurki | ah. sorry for being vague | 20:27 |
| gurki | yes, i have pure analog parts in there | 20:27 |
| tpw_rules | then yeah it sounds like you are stepping well outside of both my and litex's comfort zone. i think dumping a verilog core from vexriscv and using a flow you are familiar with might be best. that is sort of orthogonal to the question of whether to use the plugin system but unless it's one of those funky new analog neural matrix multipliers it really doesn't make sense as an instruction imo | 20:29 |
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| Advant | I'm trying to setup f4pga on macOS x64, and it's wanting certain pre-reqs that aren't available on https://conda.anaconda.org/litex-hub/osx-64, like prjxray.. is there a work around for setting this up? | 21:15 |
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