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| sensille | i might have found it, testing | 09:07 |
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| sensille | the tx slots get implemented as LUT RAM :-/ | 15:48 |
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| sensille | looks like this is an ongoing issue | 16:10 |
| sensille | FullMemoryWE makes it even worse, split into 4 memories, each implemented in LUTs | 16:37 |
| sensille | the problem seems to be in the R/W wishbone port. when i remove the read capability, it gets inferred correctly. i don't need to read the tx buffer | 17:00 |
| sensille | although it might be helpful for generating checksums | 17:02 |
| mithro | Some people here might find https://github.com/CAS-Atlantic/parmys-plugin interesting | 17:06 |
| sensille | without individual write enables it works with read/write | 17:25 |
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| mithro | https://github.com/Pitt-JonesLab/LitexDRAMTMR | 20:34 |
| mithro | https://github.com/Capstone2022Team17/drgbl | 20:44 |
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