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| MoeIcenowy | somlo: you never need to get this if you have a VC707 | 03:47 |
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| cr1901 | I wonder how I can get "gigantic FPGA board that has more resources than I can use in a lifetime" for not too much money. Even the largest FPGA board I own- lx45 or 35t- is a medium-small/medium size FPGA | 06:15 |
| sensille | a Kintex 7 XC7K325T looks like a good step in that direction | 06:37 |
| sensille | from the above mentioned store | 06:37 |
| sensille | _florent_: i misread the code, the uart does synchronize to the edge of the start bit and samples in the middle of the bittime, so only filtering could be added | 08:42 |
| MoeIcenowy | sensille: QMTECH has some more cheap 7k325t, but I choose Sitlinv one because it has some useful peripherals | 08:58 |
| MoeIcenowy | and STLV7325 has GTPs wired out | 08:59 |
| MoeIcenowy | QM 325t board just wasted them | 08:59 |
| MoeIcenowy | for Sitlinv one you can use LitePCIe, LiteSATA, LiteETH with SFP with GTPs | 08:59 |
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| MoeIcenowy | (well to be honest I used none now | 09:00 |
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| wild | on the topic of adding support for multiple BARs in litepcie, wouldnt the place to target be the address decoder fed into LitePCIeSlaveInternalPort? | 12:10 |
| wild | i know now since testing that other BAR hits will be detected and be translated, I had BAR1 read into a space that BAR0 was mapped to. | 12:11 |
| wild | the issue is decoding the incoming address for different regions. | 12:11 |
| wild | support for multiple base addresses | 12:12 |
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