| *** tpb <[email protected]> has joined #litex | 00:00 | |
| mithro | Have people here seen the work CarlFK has been doing on my behalf to enable a whole bunch of Digilent Arty A7 boards be available on the web? --> https://frontend.ps1.fpgas.mithis.com/ | 00:21 |
|---|---|---|
| *** TMM_ <[email protected]> has quit IRC (Quit: https://quassel-irc.org - Chat comfortably. Anywhere.) | 01:07 | |
| *** TMM_ <[email protected]> has joined #litex | 01:07 | |
| *** nelgau <[email protected]> has quit IRC (Ping timeout: 256 seconds) | 01:41 | |
| *** Degi_ <[email protected]> has joined #litex | 03:34 | |
| *** Degi <[email protected]> has quit IRC (Ping timeout: 256 seconds) | 03:35 | |
| *** Degi_ is now known as Degi | 03:35 | |
| *** peepsalot <peepsalot!~peepsalot@openscad/peepsalot> has quit IRC (Quit: Connection reset by peep) | 06:47 | |
| *** peepsalot <peepsalot!~peepsalot@openscad/peepsalot> has joined #litex | 06:49 | |
| *** nelgau <[email protected]> has joined #litex | 07:14 | |
| *** nelgau_ <[email protected]> has joined #litex | 07:16 | |
| *** nelgau <[email protected]> has quit IRC (Ping timeout: 260 seconds) | 07:19 | |
| *** FabM <FabM!~FabM@2a03:d604:103:600:2e60:8c7c:e8fb:7990> has joined #litex | 07:26 | |
| _florent_ | Hi mithro, that's nice yes. Is it for regression testing or to give access to developers? | 08:13 |
| _florent_ | I'm planning to put more efforts on CI with hardware in early 2023 | 08:13 |
| *** Brinx <[email protected]> has quit IRC (Remote host closed the connection) | 09:56 | |
| *** Brinx <[email protected]> has joined #litex | 09:57 | |
| *** Brinx <[email protected]> has quit IRC (Ping timeout: 256 seconds) | 10:01 | |
| *** Brinx <[email protected]> has joined #litex | 10:20 | |
| *** Brinx <[email protected]> has quit IRC (Read error: Connection reset by peer) | 10:20 | |
| *** Brinx <[email protected]> has joined #litex | 10:20 | |
| *** nelgau_ <[email protected]> has quit IRC (Ping timeout: 260 seconds) | 11:14 | |
| *** genpaku <[email protected]> has quit IRC (Remote host closed the connection) | 11:40 | |
| *** genpaku <[email protected]> has joined #litex | 11:40 | |
| *** Brinx <[email protected]> has quit IRC (Remote host closed the connection) | 11:58 | |
| *** Brinx <[email protected]> has joined #litex | 12:02 | |
| *** Brinx <[email protected]> has quit IRC (Ping timeout: 256 seconds) | 12:09 | |
| *** Brinx <[email protected]> has joined #litex | 12:33 | |
| *** TMM_ <[email protected]> has quit IRC (Quit: https://quassel-irc.org - Chat comfortably. Anywhere.) | 14:16 | |
| *** TMM_ <[email protected]> has joined #litex | 14:16 | |
| *** Brinx <[email protected]> has quit IRC (Remote host closed the connection) | 15:29 | |
| *** Brinx <[email protected]> has joined #litex | 16:13 | |
| *** Brinx <[email protected]> has quit IRC (Ping timeout: 268 seconds) | 16:18 | |
| *** FabM <FabM!~FabM@armadeus/team/FabM> has quit IRC (Remote host closed the connection) | 17:10 | |
| mithro | _florent_: I was hoping it could be used for both | 17:56 |
| mithro | _florent_: There should eventually be ~40 FPGA boards available through this | 17:57 |
| mithro | _florent_: The way I see it working is that you can "reserve" a board for a certain period. When the CI system wants to run a test, it requests a board out of the pool. | 17:58 |
| mithro | CarlFK: ^ | 17:58 |
| *** Brinx <[email protected]> has joined #litex | 18:06 | |
| *** nelgau <[email protected]> has joined #litex | 18:34 | |
| amstan | mithro: woah! i'm always interested in new boards | 19:10 |
| amstan | ah, it's a lab of boards, i get it | 19:11 |
| amstan | i saw a limited count and a "reserve" and i got excited to buy something, lol | 19:11 |
| sensille | a good reflex | 19:18 |
| amstan | i'm still looking for some kind of cute board i can use to connect over thunderbolt only to my laptop so i can do portable fpga deving with litex | 19:29 |
| sensille | not thunderbolt, but cute: https://www.crowdsupply.com/rhs-research/picoevb | 19:33 |
| tpb | Title: PicoEVB | Crowd Supply (at www.crowdsupply.com) | 19:33 |
| CarlFK | Can someone grind though the steps to make an LED blink on one of the arty boards? | 20:06 |
| *** zjason` <zjason`[email protected]> has joined #litex | 20:12 | |
| *** zjason <[email protected]> has quit IRC (Ping timeout: 256 seconds) | 20:14 | |
| *** jersey99 <[email protected]> has joined #litex | 20:34 | |
| jersey99 | _florent_When I am using Memory in simulation, with a read port in the usual "sys" clock domain, the memory_emit_verilog (in gen/fhdl/memory.py), seems to throw an error saying it can't find ClockSignal. The rest of the code seems to work with add_clocker, except Memory. Have you tried this before? Is it because Memory is a special and for some | 20:41 |
| jersey99 | reason the clock domain information isn't propagating to the code generator? | 20:41 |
| jersey99 | btw, as you can guess, this simulation is via Litex verilator, not Migen | 20:42 |
| *** thiskappaisgrey <[email protected]> has joined #litex | 20:54 | |
| *** Ian12 <[email protected]> has joined #litex | 20:56 | |
| *** Ian12 <[email protected]> has quit IRC (Client Quit) | 20:57 | |
| thiskappaisgrey | Hi, we are students at UCSB, and are trying to get OpenPiton (https://github.com/PrincetonUniversity/openpiton ) to run on litex. We managed to build it and got some of the bootloader code working but it doesn't print anything. We think it's related to the isr.c code but we aren't sure how it works. Can someone please explain? Thank you. | 20:57 |
| thiskappaisgrey | Also, the discord on the readme is expired.. | 21:00 |
| *** thanawat <[email protected]> has joined #litex | 21:05 | |
| *** thanawat <[email protected]> has quit IRC (Client Quit) | 21:07 | |
| thiskappaisgrey | sorry, I have to go.. I'll just ask again later. | 21:07 |
| *** thiskappaisgrey <[email protected]> has quit IRC (Quit: ERC 5.4 (IRC client for GNU Emacs 28.2)) | 21:07 | |
| amstan | sensille: maybe with an enclosure | 21:30 |
| amstan | though i was warned against enclosures before | 21:30 |
| sensille | amstan: why enclosure? it's just meant to be put into the laptop, or what do you mean? | 22:14 |
| amstan | i don't have room to put it inside my laptop, but i have plenty of type c thunderbolt ports | 22:15 |
| amstan | https://www.amazon.com/Thunderbolt-Certified-Tool-Free-Enclosure-EC-T3NS/dp/B08FT59SB6 | 22:15 |
Generated by irclog2html.py 2.17.2 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!